MSC8126 Freescale Semiconductor / Motorola, MSC8126 Datasheet - Page 18

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MSC8126

Manufacturer Part Number
MSC8126
Description
Quad Digital Signal Processor
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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Electrical Characteristics
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
2.5.3
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (
frequency values are not exceeded.
18
Core frequency
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
External clock frequency (CLKIN or CLKOUT)
CLKIN frequency
BCLK frequency
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
Note:
1.
2.
3.3 V
1.2 V
During time interval A,
The duration of interval A should be kept below 10 ms.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
V
The rise and fall time of external clocks should be 5 ns maximum
Characteristics
Clock and Timing Signals
Characteristic
Figure 8. Power-Up Sequence for V
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
V
A
DDH
should always be equal to or less than the
Symbol
F
F
F
F
Table 7. Maximum Frequencies
F
CLKOUT
REFCLK
CLKIN
CORE
BCLK
Table 8. Clock Frequencies
B
CLKIN
Min
200
20
40
40
40
and
400 MHz Device
V
CLKOUT
DD
/V
DDH
CCSYN
V
HCLKIN ≤ (min{100 MHz, CLKOUT})
DDH
) clocks. The user must ensure that maximum
and V
133.3
133.3
133.3
133.3
Max
400
(IO)
Maximum in MHz
V
DD
DD
/
V
/V
400/500
133/166
133/166
133/166
CCSYN
CCSYN
voltage level.
Min
200
20
40
40
40
500 MHz Device
Freescale Semiconductor
t (time)
166.7
166.7
166.7
166.7
Max
500

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