STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 98

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

DESIGN GUIDELINES
6.4.4. PCI INTERFACE
6.4.4.1. Introduction
In order to achieve a PCI interface which work at
clock
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
98/111
frequencies
up
Bridge
South
Bridge
North
Strap Options
delay
clock
to
HCLK PLL
Deskewer
MD[30:27]
33MHz,
MD[7:6]
Figure 6-28. Clock Scheme
1/2
1/3
1/4
Issue 1.0 - July 24, 2002
MD[17,4]
MUX
careful
STPC
6.4.4.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
PCICLKI
PCICLKO
HCLK
AD[31:0]
0
T
T
and T
0
1
1
.
T
2