STP2003PQFP Sun Microelectronics, STP2003PQFP Datasheet - Page 3

• Manufacturer Part Number: STP2003PQFP
• Description: PCI I/O Controller
• Manufacturer: Sun Microelectronics

PCIO
PCI I/O Controller
STP2003QFP
Bus Adapter
The Bus Adapter provides a bus-independent layer between the channel engines and the PCI bus. The PCI
bus interface is 32-bit and 33 MHz, fully compliant with the PCI Local Bus Specification, Revision 2.0. As a mas-
ter, it is capable of 64-byte (8 word) bursts. DMA writes are buffered in the Bus Adapter to support back to
back transactions.
The Bus Adapter also contains the PCI bus Configuration Space. PCIO presents itself to PCI as a multi-func-
tion device: EBus2 (a bridge) and Ethernet. Each function has its own area in the configuration space.
Channel Engine Interface
The Bus Adapter contains two identical Channel Engine Interface ports, one for each channel engine. The
Channel Engine Interface is a bus independent interface, resulting in a high level of modularity at the design
and test level.
EBus2 Channel Engine
The EBus2 Channel Engine interfaces standard off-the-shelf devices to PCIO. Up to eight single or multi-func-
tion Intel-style 8-bit devices can be accommodated with a minimum of glue logic. Four internal DMA engines
can be attached to any of these devices, buffering data streams in 128-byte FIFOs for each channel.
The standard set of IO devices is: PC87303 or SuperIO (integrates 82077 floppy controller, dual 16C550 serial
controllers for keyboard and mouse and ECP/EPP P1284 parallel port), SAB82532 serial communications
controller, CS4231 audio CODEC, MK48T59 NVRAM with alarm clock, boot PROM and USC/DSC control
port.
The EBus2 Channel Engine provides access to several general purpose IO lines (a.k.a. AUXIO), used to control
miscellaneous system functions.
Ethernet Channel Engine
The Ethernet Channel Engine provides a buffered full duplex DMA engine and a Media Access Control func-
tion based on MAC. The descriptor-based DMA engine contains independent transmit and receive channels,
each with 2048 bytes of on-chip buffering. The MAC provides a 10 or 100 Mbps CSMA/CD protocol based
network interface conforming to IEEE 802.3, proposed IEEE 802.30 and Ethernet specifications.
Scan Control Block
The Scan Control contains a tap controller.
T
S
A
YPICAL
YSTEM
PPLICATION
The following diagram shows one possible configuration of U2P and PCIO in a PCI based Ultra SPARC sys-
tem. U2P connects to the System Controller chip and other UPA ports via a UPA address, control and data
buses. The system has both PCI and EPCI slots, as well as an on board PCI device (PCIO). Interrupt informa-
tion is provided by the RIC chip, and a JTAG port is provided for board testing as well as in-circuit testing and
debugging of U2P.
August 2001
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