M25P40 Numonyx, B.V., M25P40 Datasheet
M25P40
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M25P40 Summary of contents
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... JEDEC standard two-byte signature (2013h) – RES instruction, one-byte, signature (12h), for backward compatibility ■ Packages – ECOPACK® (RoHS compliant) December 2007 4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface Rev 15 M25P40 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) 1/53 www.numonyx.com 1 ...
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... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 2/53 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 M25P40 ...
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... M25P40 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Maximum rating ...
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... SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/53 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WI M25P40 min = 2 min = 2 min = 2 ...
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... M25P40 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and VFQFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M25P40 Mbit (512 K × 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... Figure 2. SO and VFQFPN connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Section 11: Package mechanical M25P40 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/53 M25P40 ...
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... M25P40 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/53 ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P40 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... M25P40 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB ...
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... All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. 12/53 and Table 16: Instruction times (device grade ). ). PP Page Program 3)). , The CC2 M25P40 (PP), ). The BE . CC1 ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P40 features the following data protection mechanisms: ● Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... All sectors (eight sectors All sectors (eight sectors All sectors (eight sectors All sectors (eight sectors Figure 5). Unprotected area (1) All sectors (eight sectors Lower seven-eighths (seven sectors Lower half (four sectors none none none none Figure 5). M25P40 ...
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... M25P40 Figure 5. Hold condition activation C HOLD Hold Condition (standard use) Operating features Hold Condition (non-standard use) AI02029D 15/53 ...
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... Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. Table 3. Memory organization Sector 16/53 Address range 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h M25P40 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh ...
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... M25P40 Figure 6. Block diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Bytes (Page Size) X Decoder Memory organization Status Register 7FFFFh Size of the read-only memory area 000FFh AI04986 17/53 ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 18/53 Table 4. M25P40 ...
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... M25P40 Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep Power- ...
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... Write Status Register (WRSR) instruction completion ● Page Program (PP) instruction completion ● Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) instruction sequence 20/53 (Figure 8) resets the Write Enable Latch (WEL) bit Instruction D High Impedance Q M25P40 AI03750D ...
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... M25P40 6.3 Read Identification (RDID) The Read Identification (RDID) instruction is available in products with Process Technology code X only. The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (13h) ...
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... Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. 22/ BP2 Figure 10. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Table 2) becomes M25P40 b0 WIP ...
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... M25P40 Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 23/53 ...
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... Figure 11. Write Status Register (WRSR) instruction sequence 24/53 Figure 11. Table 2. The Write Status Register (WRSR) instruction also allows Instruction 7 6 High Impedance MSB M25P40 ) is W Status Register AI02282D ...
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... M25P40 Table 7. Protection modes W SRWD signal bit Software Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... High Impedance Q 1. Address bits A23 to A19 are Don’t Care. 26/53 Figure 12 Instruction 24-Bit Address MSB Data Out MSB M25P40 Data Out 2 7 AI03748D ...
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... M25P40 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 28/53 Figure 14. and Table 16: Instruction times (device grade Table 3 and Table 2) is not executed. M25P40 Instruction times 3)). ...
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... M25P40 Figure 14. Page Program (PP) instruction sequence MSB 1. Address bits A23 to A19 are Don’t Care Instruction 24-Bit Address MSB Data Byte 2 Data Byte 3 ...
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... Address bits A23 to A19 are Don’t Care. 30/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15. Table 3 and Table 2) is not executed Instruction 23 22 MSB Bit Address AI03751D M25P40 ) is SE ...
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... M25P40 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence 32/53 Table 13). Figure 17 Instruction before the supply current is reduced Stand-by Mode Deep Power-down Mode M25P40 to CC1 AI03753D ...
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... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic Signature, whose value for the M25P40 is 12h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...
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... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h. Figure 19. Release from Deep Power-down (RES) instruction sequence High Impedance Q 34/ ...
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... M25P40 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at Power-up, and then for a further delay ● Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included ...
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... V WI Write Inhibit voltage (device grade 3) 1. These parameters are characterized only. 36/53 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW threshold WI Parameter M25P40 Read Access allowed Device fully accessible time AI04009C Min. Max ...
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... M25P40 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device ...
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... Device grade 6 Device grade 3 at 55°C (1) Parameter Test condition V OUT =25 °C and a frequency of 25 MHz. A Min. Max. 2.7 3.6 2.3 3.6 –40 85 –40 125 Min. Max. 100,000 cycles per sector 10,000 20 years Min. Max M25P40 Unit V V °C Unit Unit pF pF ...
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... M25P40 Table 13. DC characteristics (device grade 6) Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I Operating current (SE) CC6 I Operating current (BE) CC7 V Input low voltage ...
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... CC / 0.9 MHz 0.9 MHz – 0 –100 µA V –0.2 CC Table 10 and Table 17 Min. Typ. 5 1.4 0.4+ n*1/256 1 4.5 M25P40 (1) Max Unit ± 2 µA ± 2 µA 100 µA 50 µ Max. ...
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... M25P40 Table 16. Instruction times (device grade 3) Symbol Alt ( °C 2. Preliminary data. 3. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ ...
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... Electronic Signature Read C min = 2 Table 10 and Table 17 Min. Typ. Max. D. 0.1 0 100 100 1 M25P40 Unit MHz MHz ns ns V/ns V/ μs (5) μs (5) μs ...
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... M25P40 Table 20. AC characteristics (50 MHz operation, device grade MHz available only in products with Process Technology code X Symbol Alt ( CLH ( CLL (3) t CLCH (3) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX ...
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... Electronic Signature Read C min = 2 Table 10 and Table 17 Min. Typ. Max. D. 0.1 0 100 100 30 30 M25P40 (1) Unit MHz MHz ns ns V/ns V/ µs µs µs ...
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... M25P40 Figure 22. Serial input timing S tCHSL C tDVCH D Q Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL tSLCH tCHDX MSB IN High Impedance High Impedance DC and ac parameters tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN tSHWL AI07439 45/53 ...
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... DC and ac parameters Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 46/53 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL M25P40 tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P40 11 Package mechanical Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package outline A2 1. Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows the position of pin 1. Table 22. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, ...
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... ddd C inches Typ Min 0.0335 0.0315 0.0000 0.0256 0.0079 0.0157 0.0138 0.2362 0.2264 0.1339 0.1260 0.1969 0.1870 0.1575 0.1496 0.0500 – 0.0039 0.0000 0.0236 0.0197 M25P40 70-ME Max 0.0394 0.0020 0.0189 0.1417 0.1693 – 0.0295 12° 0.0059 0.0039 0.0020 ...
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... Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Part numbering M25P40 – (2) . ...
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... Small text changes. Notes 2 and 3 removed from information scheme. 5.0 End timing line of t modified in SHQZ Updated Page Program (PP) instructions in 6.0 Program (PP), Instruction times (device grade 6) (device grade 3). M25P40 Changes ; DC Characteristics CC3 Table 24: Ordering Figure 25: Output timing. Page Programming, Page and Instruction times ...
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... M25P40 Table 25. Document revision history (continued) Date Revision 24-Oct-2005 22-Dec-2005 14-Apr-2006 05-Jun-2006 18-Dec-2006 25-Jan-2007 15-May-2007 50 MHz operation added (see operation, device grade 6, V ECOPACK®. Blank option removed from under 7.0 Table 24: Ordering information VFQFPN, silhouette and package mechanical drawing updated (see ...
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... Revision history Table 25. Document revision history (continued) Date Revision 26-Jun-2007 10-Dec-2007 52/53 Modified the note below Table 14 Changed test condition for I Changed clock frequency, from MHz Applied Numonyx branding. Changes 12. in Table 13. CC3 Table 20 and M25P40 Table 21. ...
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... M25P40 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...