M50FLW040AK5 STMicroelectronics, M50FLW040AK5 Datasheet
M50FLW040AK5
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M50FLW040AK5 Summary of contents
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Mbit (5 x 64KByte Blocks + 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory FEATURES SUMMARY FLASH MEMORY – Compatible with either the LPC interface or the FWH interface (Intel Spec ...
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M50FLW040A, M50FLW040B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bus Write ...
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M50FLW040A, M50FLW040B Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 32. TSOP40 – 40 lead Plastic Thin Small Outline 20mm, Package Mechanical Data . 39 PART NUMBERING . . . . . . . . . . . . . . . . . . . . ...
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M50FLW040A, M50FLW040B SUMMARY DESCRIPTION The M50FLW040 Mbit (512Kb x8) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming ...
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Figure 2. Logic Diagram (FWH/LPC Interface ID0-ID3 5 GPI0- GPI4 M50FLW040A FWH4/LFRAME M50FLW040B CLK IC RP INIT V SS Note: 1. ID3 is Reserved for Future Use (RFU) in LPC mode. Figure 3. Logic ...
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M50FLW040A, M50FLW040B Figure 4. PLCC Connections A/A Mux DQ0 FWH0/LAD0 A/A Mux Note: Pins 27 and 28 are not internally connected. Figure 5. TSOP32 Connections ...
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Figure 6. TSOP40 Connections A10 Table 3. Addresses (M50FLW040A) Block Size Address ...
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M50FLW040A, M50FLW040B SIGNAL DESCRIPTIONS There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware ...
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Program or Erase Suspend, and care should be taken to avoid this. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks from being changed. When Write Protect, WP, is ...
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M50FLW040A, M50FLW040B Table 5. Memory Identification Input Configuration (LPC mode) Memory Number V 1 (Boot memory BUS OPERATIONS The two interfaces, A/A Mux and FWH/LPC, sup- ...
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See Table 7. and Table 9., and ure 10., for a description of the Field definitions for each clock cycle of the transfer. See and Figure 15., for details on the timings of the sig- nals. Bus Abort. The Bus ...
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M50FLW040A, M50FLW040B Table 6. FWH Bus Read Field Definitions Clock Clock FWH0- Cycle Cycle Field FWH3 Number Count 1 1 START 1101b 2 1 IDSEL XXXX 3-9 7 ADDR XXXX 10 1 MSIZE XXXX 11 1 TAR 1111b 1111b 12 ...
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Table 7. FWH Bus Write Field Definitions Clock Clock Cycle Cycle Field Number Count 1 1 START 2 1 IDSEL 3-9 7 ADDR 10 1 MSIZE 11-18 M=2/4/8 DATA previous 1 TAR +1 previous 1 TAR +1 previous 1 SYNC ...
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M50FLW040A, M50FLW040B Table 8. LPC Bus Read Field Definitions (1-Byte) Clock Clock Cycle Cycle Field Number Count 1 1 START CYCTYPE DIR 3-10 8 ADDR 11 1 TAR 12 1 TAR 13-14 2 WSYNC 15 1 RSYNC ...
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Table 9. LPC Bus Write Field Definitions (1 Byte) Clock Clock Cycle Cycle Field Number Count 1 1 START CYCTY DIR 3-10 8 ADDR 11-12 2 DATA 13 1 TAR 14 1 TAR 15 1 SYNC ...
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M50FLW040A, M50FLW040B COMMAND INTERFACE All Bus Write operations to the device are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings, and verifies the ...
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Once the command is issued, subsequent Bus Read operations read the value in the Status Reg- ister. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the address falls in a ...
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M50FLW040A, M50FLW040B See Figure 27., for a suggested flowchart on using the Block Erase command. Typical Block Erase times are given in Table 18.. Sector Erase Command. The command is used to erase a Uniform 4-KByte Sec- tor, setting all ...
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Table 13. Commands Command Addr Read Memory 1+ X (2,10,11) Array Read Status 1+ X (3,10) Register Read Electronic 1+ X (10) Signature Program / Multiple Byte program 2 X (4,9,11) (FWH) Quadruple Byte Program 5 X (4,12) (A/A Mux) ...
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M50FLW040A, M50FLW040B STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The bits in the Status Register convey specific in- formation about the progress of the operation. To read the Status Register, the ...
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When the Program Suspend Status bit is ‘0’, the Program/Erase Controller is active, or has com- pleted its operation. When the bit is ‘1’, a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase ...
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M50FLW040A, M50FLW040B FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS When the Firmware Hub Interface/Low Pin Count is selected, several additional registers can be ac- cessed. These registers control the protection sta- tus of the Blocks, read the General Purpose ...
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... The signals on the FWH/LPC Interface General Purpose Input pins should remain constant throughout the whole Bus Read cycle. Manufacturer Code Register Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer Code for STMicroelectronics. This register is read-only. Writing to it has no effect. M50FLW040A, M50FLW040B (1) Function (1) ...
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M50FLW040A, M50FLW040B PROGRAM AND ERASE TIMES The Program and Erase times are shown in 18.. Table 18. Program and Erase Times Parameter Byte Program Double Byte Program Quadruple Byte Program Block Program (2) Sector Erase (4 KBytes) Block Erase (64 ...
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... Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to V less than 20ns during transitions. 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 2 ...
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M50FLW040A, M50FLW040B DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...
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Figure 12. A/A Mux Interface AC Measurement I/O Waveform Figure 13. AC Measurement Load Circuit Table 23. Impedance Symbol Parameter (1) Input Capacitance C IN (1) Clock Capacitance C CLK Recommended Pin (2) L PIN Inductance Note: 1. Sampled only, ...
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M50FLW040A, M50FLW040B Table 24. DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V (INIT) INIT Input High Voltage IH V (INIT) INIT Input Low Voltage IL (2) Input Leakage Current I LI IC, IDx ...
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Figure 14. FWH/LPC Interface Clock Waveform Table 25. FWH/LPC Interface Clock Characteristics Symbol Parameter (1) t CLK Cycle Time CYC t CLK High Time HIGH ...
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M50FLW040A, M50FLW040B Figure 15. FWH/LPC Interface AC Signal Timing Waveforms CLK FWH0-FWH3/ LAD0-LAD3 tCHFH tFLCH FWH4 START CYCLE Table 26. FWH/LPC Interface AC Signal Timing Characteristics PCI Symbol Symbol t t CLK to Data Out CHQV val CLK to Active ...
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Figure 16. Reset AC Waveforms RP, INT tPLPH W, G, FWH4/LFRAME RB Table 27. Reset AC Characteristics Symbol Parameter INIT Reset Pulse Width PLPH INIT Low to Reset PLRH RP or INIT Slew Rate ...
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M50FLW040A, M50FLW040B Figure 17. A/A Mux Interface Read AC Waveforms A0-A10 ROW ADDR VALID tAVCL tCLAX RC G DQ0-DQ7 W tPHAV RP Table 28. A/A Mux Interface Read AC Characteristics Symbol Parameter t Read Cycle Time AVAV t Row Address ...
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Figure 18. A/A Mux Interface Write AC Waveforms Write erase or program setup A0-A10 R1 tAVCL RC tWHWL tWLWH DQ0-DQ7 Table 29. A/A Mux Interface Write AC Characteristics Symbol Parameter t Write Enable Low to ...
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M50FLW040A, M50FLW040B PACKAGE MECHANICAL Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. 36/ 0.51 (.020) 1.14 (.045) R ...
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Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data Symbol Typ 7. 10. millimeters ...
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M50FLW040A, M50FLW040B Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data ...
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Figure 21. TSOP40 – 40 lead Plastic Thin Small Outline 20mm, Package Outline 1 N/2 TSOP-a Table 32. TSOP40 – 40 lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol Typ ...
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M50FLW040A, M50FLW040B PART NUMBERING Table 33. Ordering Information Scheme Example:M50FLW040 Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage 3.0 to 3.6V CC Device Function 040 ...
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APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE Table 34. M50FLW040A Block Addresses Block Block Sector Address Size No and Size Range (KByte) Type (KByte) 7F000h- 4 7FFFFh 7E000h- 4 7EFFFh 7D000h- 4 7DFFFh 7C000h- 4 7CFFFh 7B000h- 4 7BFFFh 7A000h- ...
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M50FLW040A, M50FLW040B Block Block Sector Address Size No and Size Range (KByte) Type (KByte) 0F000h- 4 0FFFFh 0E000h- 4 0EFFFh 0D000h- 4 0DFFFh 0C000h- 4 0CFFFh 0B000h- 4 0BFFFh 0A000h- 4 0AFFFh 09000h- 4 09FFFh 08000h- 4 08FFFh 0 64 ...
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Block Block Sector Address Size No and Size Range (KByte) Type (KByte) 1F000h- 4 1FFFFh 1E000h- 4 1EFFFh 1D000h- 4 1DFFFh 1C000h- 4 1CFFFh 1B000h- 4 1BFFFh 1A000h- 4 1AFFFh 19000h- 4 19FFFh 18000h- 4 18FFFh 1 64 (Main) 17000h- ...
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M50FLW040A, M50FLW040B APPENDIX B. FLOWCHARTS AND PSEUDO CODES Figure 22. Program Flowchart and Pseudo Code Start Write 40h or 10h Write Address and Data Read Status Register SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES FWH/LPC ...
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Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only) Start Write 40h or 10h Write Start Address and 2/4 Data Bytes (3) Read Status Register SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES ...
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M50FLW040A, M50FLW040B Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write ...
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Figure 25. Program Suspend and Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR2 = 1 YES Write a read Command Read data from another address Write D0h Program Continues Note: ...
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M50FLW040A, M50FLW040B Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 80h Write 10h Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES End ...
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Figure 27. Sector/Block Erase Flowchart and Pseudo Code Start Write 20h/32h Write Block Address and D0h Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES FWH/LPC Interface SR1 = ...
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M50FLW040A, M50FLW040B Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register SR7 = 1 YES SR6 = 1 YES Read data from another block/sector or Program Write D0h Erase Continues 50/52 ...
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REVISION HISTORY Table 36. Document Revision History Date Version 23-Jun-2003 1.0 04-Jul-2003 2.0 28-Jul-2003 2.1 08-Oct-2003 2.2 07-Nov-2003 2.3 18-Feb-2004 3.0 18-May-2004 4.0 18-Aug-2004 5.0 Revision Details First Issue V (INIT) min parameter modified in IH Document status promoted from ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...