MSDC22D-38KX3 Kingmax Semiconductor, MSDC22D-38KX3 Datasheet - Page 10

• Manufacturer Part Number: MSDC22D-38KX3
• Description: DRAM Module, 512 MB PC-2100 DDR SO-DIMM
• Manufacturer: Kingmax Semiconductor

COMMAND TRUTH TABLE
Note : 1. OP Code : Operand Code. A
Kingmax - Memory Module
Register
Register
Refresh
Bank Active & Row Address
Read &
Column Address Auto Precharge Enable
Write &
Column Address Auto Precharge Enable
Burst Stop
Precharge
Active Power Down
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
2. EMRS/ MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA
5. If A
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges
9. This combination is not defined for any function, which means "No Operation (NOP)" in DDR
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatically precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If both BA
If both BA
If both BA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
(Write DM latency is 0).
SDRAM.
0
10
~ BA
/AP is "High" at row precharge, BA
Command
Extended MRS
Mode Register Set
Auto Refresh
Self Refresh
Auto Precharge Disable
Auto Precharge Disable
Bank Selection
All Banks
1
0
0
0
0
: Bank select addresses.
and BA
is "High" and BA
is "Low" and BA
and BA
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
Entry
Entry
Entry
Exit
Exit
Exit
0
1
1
~ A
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
CKE
11
H
H
H
H
H
H
H
H
H
H
H
H
& BA
L
L
L
n-1
0
and BA
CKE
0
X
X
H
H
X
X
X
X
X
H
H
X
L
L
L
~ BA
n
1
1
/CS /RAS /CAS /WE BA
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
: Program keys. (@EMRS/MRS)
are ignored and all banks are selected.
10
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
512MB PC-2100 DDR SO-DIMM
H
X
H
H
H
X
X
X
H
X
X
X
H
L
L
L
L
L
V
V
H
X
H
H
H
X
X
X
H
X
X
H
L
L
L
L
L
V
V
H
H
X
H
H
X
X
X
H
X
X
H
L
L
L
L
L
V
V
X
V
V
V
V
0,1
MSDC22D-38KX3
May 2002 Rev: 1.0
A
10
OP code
OP code
H
H
H
L
L
L
/AP
Row address
X
X
X
X
X
X
X
A12,A
(A
(A
Column
Column
address
address
A
9
0
0
X
~A
~A
~A
11
0
9
9
)
)
,
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9