N74F827D,602 NXP Semiconductors, N74F827D,602 Datasheet
N74F827D,602
Specifications of N74F827D,602
N74F827D
N74F827D
Related parts for N74F827D,602
N74F827D,602 Summary of contents
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Rev. 04 — 29 January 2010 1. General description The 74F827 10-bit buffer, provides high performance bus interface buffering for wide data/address paths or buses carrying parity. The device has NOR output enables (OE0, ...
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... NXP Semiconductors 4. Functional diagram OE0 13 OE1 Fig 1. Logic symbol A0 1 OE0 13 OE1 Y0 Fig 3. Logic diagram 74F827_4 Product data sheet 001aae885 Fig Rev. 04 — 29 January 2010 10-bit buffer/line driver; non-inverting; 3-state 1 & EN1 001aae886 IEC logic symbol 001aae887 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin OE0 10, 11 GND 12 OE1 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output [1] One FAST Unit Load (UL) is defined as 20 74F827_4 Product data sheet 10-bit buffer/line driver; non-inverting; 3-state ...
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... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function selection Input OEn [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I HIGH-level input current LOW-level input current IL I OFF-state output current output current O I supply current CC [1] All typical values are measured at V [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter Conditions t HIGH to LOW An to Yn; see PHL propagation delay t OFF-state to HIGH OEn to Yn; see PZH propagation delay t OFF-state to LOW OEn to Yn; see PZL propagation delay t HIGH to OFF-state OEn to Yn; see ...
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... NXP Semiconductors OEn input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay 3-state output enable time to LOW-level and output disable time from LOW-level 74F827_4 Product data sheet 10-bit buffer/line driver ...
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... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data and V levels are given in EXT R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 7. Test circuit for measuring switching times Table 8 ...
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... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 9. Package outline SOT340-1 (SSOP24) ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP 24 (SOT222-1) package removed from 12 “Package outline” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...