74LVT543PW,118 NXP Semiconductors, 74LVT543PW,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVT543PW,118
• Description: IC TRANSCVR 8BIT N-INV 24TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT543PW,118

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT543PW-T; 74LVT543PW-T; 935177720118

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
1998 Feb 19
Combines 74LVT245 and 74LVT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64mA/–32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
3.3V Octal latched transceiver with dual enable
(3-State)
SYMBOL
I
t
t
C
C
PLH
PHL
CCZ
I/O
IN
PACKAGES
OEBA
LEBA
GND
EAB
A2
A3
A6
A7
A0
A1
A4
A5
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
10
11
12
1
2
3
4
5
6
7
8
9
PARAMETER
24
23
22
21
20
19
18
17
16
15
14
13
TEMPERATURE RANGE
SV00026
V
EBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
OEAB
CC
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
C
V
V
Outputs disabled; V
Outputs disabled; V
L
CC
I
OUTSIDE NORTH AMERICA
= 0V or 3.0V
= 50pF;
= 3.3V
2
T
DESCRIPTION
The 74LVT543 is a high-performance BiCMOS product designed for
V
This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.
FUNCTIONAL DESCRIPTION
The 74LVT543 contains two sets of eight D–type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
LOGIC SYMBOL
74LVT543 PW
74LVT543 DB
amb
74LVT543 D
CC
operation at 3.3V.
CONDITIONS
= 25 C; GND = 0V
I/O
CC
23
14
= 0V or 3.0V
11
= 3.6V
1
EAB
EBA
LEAB
LEBA
A0 A1 A2 A3
B0 B1 B2
22
3
21
NORTH AMERICA
4
74LVT543PW DH
74LVT543 DB
20
74LVT543 D
5
B3
19
6
B4 B5 B6
A4 A5 A6 A7
18
7
17
8
TYPICAL
OEAB
OEBA
16
9 10
0.13
2.3
3.0
10
4
B7
15
Product specification
74LVT543
SV00027
DWG NUMBER
853-1749 18988
SOT137-1
SOT340-1
SOT355-1
13
2
UNIT
mA
pF
pF
ns