74LVC2952AD,112 NXP Semiconductors, 74LVC2952AD,112 Datasheet

IC REGISTERED TXRX 8BIT 24SOIC

74LVC2952AD,112

Manufacturer Part Number
74LVC2952AD,112
Description
IC REGISTERED TXRX 8BIT 24SOIC
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2952APW118.pdf (19 pages)

Specifications of 74LVC2952AD,112

Logic Type
Registered Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC2952AD
74LVC2952AD
935251340112
1. General description
2. Features
The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back-to-back
registers store data flowing in both directions between two bidirectional buses. Data
applied to the inputs is entered and stored on the rising edge of the clock (CPAB, CPBA)
provided that the clock enable (CEAB, CEBA) input is LOW. The data is then present at
the 3-state output buffers, but is only accessible when the output enable (OEAB, OEBA)
input is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.
74LVC2952A
Octal registered transceiver with 5 V tolerant inputs/outputs;
3-state
Rev. 02 — 29 June 2004
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Flow-through pin-out architecture
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C.
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Product data sheet

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74LVC2952AD,112 Summary of contents

Page 1

Octal registered transceiver with 5 V tolerant inputs/outputs; 3-state Rev. 02 — 29 June 2004 1. General description The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Inputs ...

Page 2

Philips Semiconductors 3. Quick reference data Table 1: GND = Symbol PHL PLH f max I [ input frequency in MHz; ...

Page 3

Philips Semiconductors 5. Functional diagram Fig 1. Functional diagram. 9397 750 13251 Product data sheet OEAB 15 OEBA 11 CEAB 13 CEBA 10 ...

Page 4

Philips Semiconductors 9 11 OEAB CEAB 10 CPAB OEBA CEBA 15 13 Fig 2. Logic symbol. 6. Pinning information 6.1 Pinning Fig 4. Pin ...

Page 5

Philips Semiconductors 6.2 Pin description Table 3: Symbol OEAB CPAB CEAB GND CEBA CPBA OEBA 9397 750 13251 Product data sheet Pin ...

Page 6

Philips Semiconductors 7. Functional description 7.1 Function table Table 4: Operating mode Hold data Load data Load data Table 5: Operating mode Disable outputs Enable outputs Enable outputs [ HIGH voltage level LOW voltage level; Z ...

Page 7

Philips Semiconductors 9. Recommended operating conditions Table 7: Symbol amb 10. Static characteristics Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = ...

Page 8

Philips Semiconductors Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V ...

Page 9

Philips Semiconductors Table 9: Dynamic characteristics GND = 0 V; see Figure 8 for test circuit. Symbol Parameter 3-state output disable time PHZ PLZ OEBA, OEAB to An and Bn t clock pulse width HIGH or LOW ...

Page 10

Philips Semiconductors Table 9: Dynamic characteristics GND = 0 V; see Figure 8 for test circuit. Symbol Parameter 3-state output disable time PHZ PLZ OEBA, OEAB to An clock pulse width HIGH or LOW CPAB ...

Page 11

Philips Semiconductors 12. Waveforms Fig 5. Clock input (CPBA, CPAB) to output (An, Bn) propagation delays, the clock pulse Table 10: Supply voltage V CC 2.7 V 2.7 V Fig 6. Set-up and hold times for the An, Bn and ...

Page 12

Philips Semiconductors Fig 7. 3-state enable and disable times. Table 12: Supply voltage V CC 2.7 V 2.7 V 9397 750 13251 Product data sheet V I OExx input V M GND t PLZ V CC output LOW-to-OFF OFF-to-LOW V ...

Page 13

Philips Semiconductors Fig 8. Load circuitry for switching times. Table 13: Supply voltage V CC 1.2 V 2 3.6 V [1] The circuit performs better when R 9397 750 13251 Product data sheet V I PULSE ...

Page 14

Philips Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 15

Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

Page 16

Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 17

Philips Semiconductors 14. Revision history Table 14: Revision history Document ID Release date 74LVC2952A_2 20040629 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • Table ...

Page 18

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 19

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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