74LVC162244ADL,118 NXP Semiconductors, 74LVC162244ADL,118 Datasheet - Page 2
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74LVC162244ADL,118
Manufacturer Part Number
74LVC162244ADL,118
Description
IC BUFF DVR TRI-ST 16BIT 48SSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC162244ADGG11.pdf
(16 pages)
Specifications of 74LVC162244ADL,118
Package / Case
48-SSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
16
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 12 mA
Input Bias Current (max)
80 uA
Low Level Output Current
12 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
11 ns (Typ) @ 1.2 V or 3 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
16 / 16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC162244ADL-T
74LVC162244ADL-T
935237670118
74LVC162244ADL-T
935237670118
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 Dec 12
t
t
t
C
C
PHL
PZH
PHZ
SYMBOL
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Integrated 30
All data inputs have bushold (74LVCH162244A only)
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
16-bit buffer/line driver, 30
resistors; 5 V tolerant input/output; 3-state
P
f
f
C
V
N = total load switching outputs;
i
o
/t
/t
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
PZL
PLZ
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay nAn to nYn
3-state output enable time nOE to nYn
3-state output disable time nOE to nYn
input capacitance
power dissipation capacitance per gate
2
V
CC
= 25 C; t
termination resistors
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
r
PARAMETER
= t
f
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
series termination
C
C
C
V
CC
L
L
L
2
outputs enabled
outputs disabled
= 50 pF; V
= 50 pF; V
= 50 pF; V
DESCRIPTION
The 74LVC(H)162244A is a high-performance, low power,
low voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices as a mixed 3.3 and 5 V environment.
The 74LVC(H)162244A is a 16-bit non-inverting buffer/line
driver with 3-state outputs. The device can be used as four
4-bit buffers, two 8-bit buffers or one 16-bit buffer. The
3-state outputs are controlled by the output enable inputs
1OE, 2OE, 3OE and 4OE. A HIGH on nOE causes the
outputs to assume a high-impedance OFF-state.
The 74LVCH162244A bushold data inputs eliminates the
need for external termination resistors to hold unused
inputs.
The 74LVC(H)162244A is designed with 30
termination resistors in both HIGH and LOW output stages
to reduce line noise.
= 3.3 V; notes 1 and 2
D
in W).
CONDITIONS
CC
CC
CC
= 3.3 V
= 3.3 V
= 3.3 V
74LVCH162244A
74LVC162244A;
3.0
3.5
2.8
5.0
12
4.0
TYPICAL
Product specification
ns
ns
ns
pF
pF
pF
series
UNIT