74ABT125PW,112 NXP Semiconductors, 74ABT125PW,112 Datasheet - Page 3

IC BUFF TRI-ST QD N-INV 14TSSOP

74ABT125PW,112

Manufacturer Part Number
74ABT125PW,112
Description
IC BUFF TRI-ST QD N-INV 14TSSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet

Specifications of 74ABT125PW,112

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Logic Family
ABT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 4
Output Type
3-State
Propagation Delay Time
4.6 ns at 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ABT125PW
74ABT125PW
935201060112
NXP Semiconductors
Table 2.
6. Functional description
Table 3.
[1]
7. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
[2]
[3]
74ABT125
Product data sheet
Symbol
1OE to 4OE
1A to 4A
1Y to 4Y
GND
V
Inputs
nOE
L
L
H
Symbol
V
V
V
I
I
I
T
T
P
IK
OK
O
j
stg
CC
CC
I
O
tot
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
SO14 packages: above 70 C P
SSOP14 and TSSOP20 packages: above 60 C P
DHVQFN14 packages: above 60 C P
Pin description
Function selection
Limiting values
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
total power dissipation
5.2 Pin description
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
[1]
[1]
tot
derate linearly with 8 mW/K
tot
derate linearly with 4.5 mW/K
nA
L
H
X
All information provided in this document is subject to legal disclaimers.
V
output in LOW-state
T
Conditions
output in OFF-state or HIGH-state
V
Rev. 5 — 24 November 2010
tot
amb
I
O
< 0 V
derate linearly with 5.5 mW/K
< 0 V
= 40 C to +85 C
Description
output enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
Output
nY
L
H
Z
[2]
[3]
Min
0.5
1.2
0.5
18
50
-
-
65
-
74ABT125
Quad buffer; 3-state
+7.0
+7.0
-
128
+150
Max
+5.5
-
150
500
© NXP B.V. 2010. All rights reserved.
Unit
V
V
V
mA
mA
mA
C
C
mW
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