74ALVCH16244T Fairchild Semiconductor, 74ALVCH16244T Datasheet
74ALVCH16244T
Specifications of 74ALVCH16244T
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74ALVCH16244T Summary of contents
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... CMOS power dissipation. Ordering Code: Package Order Number Number 74ALVCH16244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © ...
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Connection Diagram Functional Description The 74ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. The control pins may be shorted together to ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 2) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay 1.0 PHL PLH Output Enable Time 1.0 PZL PZH Output Disable Time 1.0 PLZ PHZ Capacitance Symbol Parameter C Input Capacitance ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...