ADSP-21062KS-133 Analog Devices, ADSP-21062KS-133 Datasheet
ADSP-21062KS-133
Specifications of ADSP-21062KS-133
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ADSP-21062KS-133 Summary of contents
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... DUAL-PORTED BLOCKS 32 x 48-BIT PROCESSOR PORT ADDR DATA ADDR PROGRAM SEQUENCER 40/32 ALU Figure 1. ADSP-21062/ADSP-21062L Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L I/O PORT EMULATION DATA ADDR DATA DATA ADDR ...
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... Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25 Figure 17. Multiprocessor Bus Request and Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28 Figure 18b. Asynchronous Read/Write—Host to ADSP-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion Figure 19b. Three-State Timing (Host Transition Cycle Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 32 Figure 21 ...
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... DSP core with integrated, on-chip system features REV. B ADSP-21062/ADSP-21062L including a 2 Mbit SRAM memory (4 Mbit on the ADSP-21060), host processor interface, DMA controller, serial ports and link port and parallel bus connectivity for glueless DSP multiprocessing. ...
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... DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the ADSP- 21062’s external port. –4– REV. B ...
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... Maxi- mum throughput for interprocessor data transfer is 240 Mbytes/s over the link ports or external port. Broadcast writes allow simulta- neous transmission of data to all ADSP-21062s and can be used to implement reflective semaphores. Link Ports The ADSP-21062 features six 4-bit link ports that provide addi- tional I/O capabilities ...
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... ADSP-21062/ADSP-21062L 1x CLOCK RESET Figure 3. Shared Memory Multiprocessing System ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 011 ID 2-0 CONTROL CPA 1-2 4 ADSP-2106x #2 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 010 ID 2-0 CONTROL CPA 3 ADSP-2106x #1 CLKIN ADDR 31-0 RESET DATA 47-0 RD RPBA WR 3 ACK ...
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... Circuit Emulator, EZ-LAB development board, EZ-KIT, and development software. The EZ-LAB contains an evaluation board with an ADSP-21062 (5 V) processor and provides a serial connec- tion to your PC. The SHARC EZ-KIT combines the ADSP- 21000 Family Development Software for the PC and the EZ-LAB ADSP-21062’s Development Board in one package. ...
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... WR is not later asserted (e.g conditional write instruction multiprocessing system output by the bus master and is input by all other ADSP-21062s to determine if the multiprocessor memory access is a read or write asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the ADSP-21062(s) ...
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... Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con- figuration selection which must be set to the same value on every ADSP-21062. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21062. ...
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... TRST Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power- I held low for proper operation of the ADSP-21062. TRST has internal pull-up resistor. EMU O Emulation Status. Must be connected to the ADSP-21062 EZ-ICE target board connector only. ...
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... BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted after power-up (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the BXXX pins (Pins 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as follows: ...
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... EMU should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. If TCK, TMS, and CLKIN are driving a large number of ADSP- 21062s (more than eight) in your system, then treat them as a “clock tree” using multiple drivers to minimize skew. (See Figure 7 “ ...
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... Max 2 4 150 10 10 350 1.5 350 4.2 150 = 2 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21062 is 2-0 = 001 and another 2-0 Units RPBA, 2-0 Units ...
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... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21062L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
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... V 4 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21062 is 2-0 = 001 and another 2-0 Units 0 0 RPBA, 6-1 2-0 Units ...
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... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21062L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21062 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Only required if multiple ADSP-21062s must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-21062s communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset. ...
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... Enable 3 OUT Disable 14 OUT t DFO t DFO t HFO FLAG OUTPUT t HFI t SFI t HFIWR Figure 12. Flags –19– ADSP-21062/ADSP-21062L ADSP-21062L Min Max 15 t DTEX ADSP-21062L Min Max 8 + 5DT/16 0 – 5DT/ 7DT/ DFOD Units ns Units ...
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... ADSP-21062/ADSP-21062L Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t Address, Selects Delay to Data Valid ...
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... Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t ACK Delay from Address, Selects ...
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... When accessing a slave ADSP-21062, these switching character- istics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21062 must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. ADSP-21062 ...
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... CLKIN t DADCCK ADRCLK t DADRO ADDRESS MSx, SW PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) REV ADRCKH t DAAK t DPGC t DRWL t DRWL t SDDATO Figure 15. Synchronous Read/Write—Bus Master –23– ADSP-21062/ADSP-21062L t ADRCK t ADRCKL t HADRO t HACK t SACKC t DRDO t HSDATI t SSDATI t DWRO t DATTR ...
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... ADSP-21062/ADSP-21062L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21062 bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor Parameter Timing Requirements: Address, SW Setup Before CLKIN t SADRI Address, SW Hold Before CLKIN t HADRI RD/WR Low Setup Before CLKIN t SRWLI RD/WR Low Hold After CLKIN ...
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... CLKIN ADDRESS SW ACK READ ACCESS RD DATA (OUT) WRITE ACCESS WR DATA (IN) REV SADRI t DACKAD t SRWLI t SDDATO t SRWLI Figure 16. Synchronous Read/Write—Bus Slave –25– ADSP-21062/ADSP-21062L t HADRI t ACKTR t t HRWLI RWHPI t DATTR t t RWHPI HRWLI t HDATWH t SDATWH ...
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... NOTES For first asynchronous access after HBR and CS asserted, ADDR 1 low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition. 2 Only required for recognition in the current cycle. ...
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... HBR AND CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 17. Multiprocessor Bus Request and Host Bus Request REV HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SHBGI t SBRI t HRPBAI t TRDYHG t HBGRCSV –27– ADSP-21062/ADSP-21062L t TRCPA t HHBGI t HBRI t ARDYTR ...
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... WR goes low after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces- HBGRCSV sor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition. CLKIN REDY (O/D) REDY (A/D) drive the RD and WR pins to access the ADSP-21062’ ...
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... READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 18b. Asynchronous Read/Write—Host to ADSP-21062 REV SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL t WWRL t t DRDYWRL RDYPWR –29– ADSP-21062/ADSP-21062L t HADRDH t WRWH ...
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... DT/8 8 – STSCK t HTSCK t t MIENA, MIENS, MIENHG t DATEN t ACKEN ADCEN t MENHBG –30– ADSP-21062L Min Max DT/2 –1.25 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT 5DT/16 –0.5 – DT/8 7 – DT/8 7.5 + DT/4 –1 – DT/8 6 – DT/8 –2 – DT/8 8 – ...
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... DT/ DT/ 9DT/ 3DT –0 –31– ADSP-21062/ADSP-21062L , and ACK 3-0 , RD, WR, 31-0 ADSP-21062L Min Max 5DT 7DT 7DT DT DT 3DT 5DT/8 –2 – DT/8 6 – DT 9DT/ –0. 5DT DT/16 ...
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... ADSP-21062/ADSP-21062L CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ...
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... /2) – 1. / DT/2 and –33– ADSP-21062/ADSP-21062L ADSP-21062L Min Max DT/2 28.5 + DT/2 – DT DT/2 18 –7 15.5 2.5 –3 (t /2) – / /2) – 1 ...
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... The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21062 Setup Skew LCLKTWH ADSP-21062 Hold Skew ADSP-21062L Setup Skew = 2.10 ns max ADSP-21062L Hold Skew = 1.87 ns max ADSP-21062 Min Max 2.5 2.25 t ...
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... LINK PORT ENABLE OR THREE-STATE TAKES EFFECT TWO CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER. LINK PORT INTERRUPT SETUP TIME CLKIN t SLCK LCLK LACK REV. B LAST NIBBLE FIRST NIBBLE TRANSMITTED TRANSMITTED t t SLACH HLACH t LCLKIW t LCLKRWL t HLDCL t SLDCL IN t TDLK t HLCK Figure 21. Link Ports –35– ADSP-21062/ADSP-21062L LCLK INACTIVE (HIGH) t DLACLK t DLALC ...
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... SCLK SCLK 3 4. 3DT 12.75 3.5 –36– ADSP-21062L Min Max Units 3 1 4.5 ns –1 ...
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... CLKIN SPORT ENABLE AND THREE-STATE LATENCY TFS (EXT) IS TWO CYCLES NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING. Figure 22. Serial Ports –37– ADSP-21062/ADSP-21062L DRIVE SAMPLE EDGE EDGE t SCLKW t DFSE t HOFSE ...
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... ADSP-21062/ADSP-21062L RCLK RFS DT TCLK TFS DT EXTERNAL RFS with MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t (SEE NOTE 2 HOFSE/I ON PREVIOUS PAGE) t SFSE/I t DDTE DDTENFS HDTE/I 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t (SEE NOTE 2 HOFSE/I ON PREVIOUS PAGE) t SFSE/I t DDTE DDTENFS ...
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... LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 3-0 , RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2 LxCLK, LxACK, BMS. 3-0 t TCK t t STAP HTAP t DTDO t DSYS Figure 24. IEEE 11499.1 JTAG Test Access Port –39– ADSP-21062/ADSP-21062L ADSP-21062L Max Min Max 18 18.5 18.5 , RPBA, IRQ , ID ...
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... ADSP-21062/ADSP-21062L OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21062. The curves represent the current drive capability of the output drivers as a function of output voltage. POWER DISSIPATION Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers ...
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... To determine the data output hold time in a particular system, first calculate t using the equation given above. Choose V DECAY to be the difference between the ADSP-21062’s output voltage and the input threshold for the device requiring the hold time. A typical V will be 0 the total bus capacitance (per ...
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... Maximum Case Temperature) (V 120 100 –20 –40 –60 –80 –100 –120 140 160 180 200 Figure 32. ADSP-21062 Typical Drive Currents ( FALL TIME 140 160 180 200 Figure 33. Typical Output Rise Time (10%–90% V Load Capacitance (V –42– 5 ...
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... Maximum Case Temperature) (V REV. B ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP-21062 is available in 240-lead thermally enhanced MQFP and 225-lead plastic ball grid array packages. The top surface of the thermally enhanced MQFP contains a copper slug from which most of the die heat is dissipated. The slug is flush with the top surface of the package ...
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... ADSP-21062/ADSP-21062L 225-Ball Plastic Ball Grid Array (PBGA) Package Descriptions Ball # Name Ball # BMS A01 D01 A02 ADDR30 D02 DMAR2 A03 D03 A04 DT1 D04 A05 RCLK1 D05 A06 TCLK0 D06 A07 RCLK0 D07 A08 ADRCLK D08 CS A09 D09 A10 CLKIN D10 ...
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... L3DAT0 L4DAT2 L5DAT2 L5ACK L1ACK L2DAT0 L3DAT3 L3CLK L4CLK L5DAT1 L2DAT2 L2CLK L3DAT2 L4DAT3 L4DAT0 L5DAT3 L2DAT1 L2ACK L3DAT1 L3ACK L4DAT1 L4ACK –45– ADSP-21062/ADSP-21062L DMAR2 BMS DT1 RCLK1 ADDR30 B HBR MS0 SW DR1 ADDR31 C SBTS MS3 MS1 TCLK1 ...
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... ADSP-21062/ADSP-21062L 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.101 (2.57) 0.091 (2.32) 0.081 (2.06) NOTES 1.THE ACTUAL POSITION OF THE BALL ARRAY IS WITHIN 0.12 (0.30) OF ITS IDEAL POSITION RELATIVE TO THE EDGE OF THE PACKAGE. 2.THE ACTUAL POSITION OF ANY BALL IS WITHIN 0.004 (0.10) OF ITS IDEAL POSITION RELATIVE TO THE ARRAY OF BALLS. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). ...
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... DATA45 155 116 VDD 156 117 DATA44 157 118 DATA43 158 119 DATA42 159 120 GND 160 –47– ADSP-21062/ADSP-21062L 181 180 121 120 Pin Pin Pin No. Name Name 161 DATA14 DATA41 162 DATA13 DATA40 DATA39 163 DATA12 164 ...
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... LEAD PITCH 0.01969 (0.50) TYP LEAD WIDTH 0.011 (0.27) 0.009 (0.22) TYP 0.007 (0.17) 0.004 (0.10) MAX 0.010 (0.25) MIN Case Part Number Temperature Range ADSP-21062KS-133 +85 C ADSP-21062KS-160 +85 C ADSP-21062KB-160 +85 C ADSP-21062CS-160 – +100 C ADSP-21062LKS-133 +85 C ADSP-21062LKS-160 +85 C ADSP-21062LKB-160 +85 C ADSP-21062LAB-160 – ...