ADSP-21062 Analog Devices, ADSP-21062 Datasheet
ADSP-21062
Specifications of ADSP-21062
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ADSP-21062 Summary of contents
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... INSTRUCTION TWO INDEPENDENT CACHE DUAL-PORTED BLOCKS 32 x 48-BIT PROCESSOR PORT ADDR DATA ADDR PROGRAM SEQUENCER 40/32 ALU ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L I/O PORT EMULATION DATA ADDR DATA ADDR DATA EXTERNAL IOD IOA PORT 48 17 ADDR BUS MUX MULTIPROCESSOR INTERFACE ...
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... Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25 Figure 17. Multiprocessor Bus Request and Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28 Figure 18b. Asynchronous Read/Write—Host to ADSP-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion Figure 19b. Three-State Timing (Host Transition Cycle Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 32 Figure 21 ...
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... Mbit SRAM memory (4 Mbit on the ADSP-21060), host processor interface, DMA controller, serial ports and link port and parallel bus connectivity for glueless DSP multiprocessing. Figure 1 shows a block diagram of the ADSP-21062, illustrating the following architectural features: Computation Units (ALU, Multiplier and Shifter) with a Shared Data Register File ...
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... The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle. On the ADSP-21062, the memory can be configured as a maxi- mum of 64K words of 32-bit data, 128K words of 16-bit data, 40K words of 48-bit instructions (or 40-bit data), or combina- tions of different word sizes up to two megabits ...
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... Maxi- mum throughput for interprocessor data transfer is 240 Mbytes/s over the link ports or external port. Broadcast writes allow simulta- neous transmission of data to all ADSP-21062s and can be used to implement reflective semaphores. Link Ports The ADSP-21062 features six 4-bit link ports that provide addi- tional I/O capabilities ...
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... ADSP-21062/ADSP-21062L 1x CLOCK RESET ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 011 ID 2-0 CONTROL CPA 1-2 4 ADSP-2106x #2 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 010 ID 2-0 CONTROL CPA 3 ADSP-2106x #1 CLKIN ADDR 31-0 RESET DATA 47-0 RD RPBA WR 3 ACK ...
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... Circuit Emulator, EZ-LAB development board, EZ-KIT, and development software. The EZ-LAB contains an evaluation board with an ADSP-21062 (5 V) processor and provides a serial connec- tion to your PC. The SHARC EZ-KIT combines the ADSP- 21000 Family Development Software for the PC and the EZ-LAB ADSP-21062’s Development Board in one package. ...
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... I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-21062 writes to external memory devices or to the internal memory of other ADSP-21062s. External devices must assert WR to write to the ADSP-21062’s internal memory multiprocessing system WR is output by the bus master and is input by all other ADSP-21062s. ...
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... Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con- figuration selection which must be set to the same value on every ADSP-21062. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21062. ...
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... TRST Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power- I held low for proper operation of the ADSP-21062. TRST has a 20 kΩ internal pull-up resistor. EMU O Emulation Status. Must be connected to the ADSP-21062 EZ-ICE target board connector only. ...
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... EZ-ICE probe is turned on by the emulator at software start-up. After software start-up, TRST is driven high. JTAG ADSP-2106x DEVICE #1 (OPTIONAL) TDI TDI TDO TDI EZ-ICE JTAG CONNECTOR TCK TMS EMU TRST TDO CLKIN OPTIONAL ADSP-21062/ADSP-21062L ADSP-2106x n TDO TDI TDO ...
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... ADSP-21062/ADSP-21062L Figure 6 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors. Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping, and single-stepping mul- tiple ADSP-2106xs in a synchronous manner. If you do not need these operations to occur synchronously on the multiple proces- sors, simply tie Pin 4 of the EZ-ICE header to ground ...
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... V 4 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21062 is 2-0 = 001 and another 2-0 Units V ° RPBA, 2-0 Units V V µA µ ...
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... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21062L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
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... V 4 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21062 is 2-0 = 001 and another 2-0 Units V ° RPBA, 2-0 Units ...
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... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21062L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21062 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Only required if multiple ADSP-21062s must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-21062s communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset. ...
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... RD, WR FLAG INPUT ADSP-21062 Min Max 15 ADSP-21062 Min Max 5DT/ – 5DT/ 7DT/ Enable 3 OUT Disable 14 OUT t DFO t DFO t HFO FLAG OUTPUT t HFI t SFI t HFIWR ADSP-21062/ADSP-21062L ADSP-21062L Min Max 15 t DTEX ADSP-21062L Min Max 8 + 5DT/16 0 – 5DT/ 7DT/ DFOD Units ns Units ...
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... ADSP-21062/ADSP-21062L Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t Address, Selects Delay to Data Valid ...
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... Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing external memory space. These switching Parameter Timing Requirements: t ACK Delay from Address, Selects ...
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... When accessing a slave ADSP-21062, these switching character- istics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21062 must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. ADSP-21062 ...
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... CLKIN t DADCCK ADRCLK t DADRO ADDRESS MSx DPGC PAGE ACK (IN) READ CYCLE t DRWL RD DATA (IN) WRITE CYCLE t DRWL WR t SDDATO DATA (OUT) ADSP-21062/ADSP-21062L t ADRCK t ADRCKH t DAAK t SACKC t SSDATI t ADRCKL t HADRO t HACK t DRDO t HSDATI t DWRO t DATTR ...
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... ADSP-21062/ADSP-21062L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21062 bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor Parameter Timing Requirements: Address, SW Setup Before CLKIN t SADRI Address, SW Hold Before CLKIN t HADRI RD/WR Low Setup Before CLKIN t SRWLI RD/WR Low Hold After CLKIN ...
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... CLKIN ADDRESS SW ACK READ ACCESS RD t SDDATO DATA (OUT) WRITE ACCESS WR DATA (IN) ADSP-21062/ADSP-21062L t SADRI t HADRI t DACKAD t t SRWLI HRWLI t t SRWLI HRWLI t HDATWH t SDATWH t ACKTR t RWHPI t DATTR t RWHPI ...
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... NOTES 1 For first asynchronous access after HBR and CS asserted, ADDR low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition. 2 Only required for recognition in the current cycle. ...
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... HBG (OUT) BRx (OUT) CPA (OUT) (O/D) HBG (IN) BRx (IN) CPA (IN) (O/D) t SRPBAI RPBA HBR AND CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE ADSP-21062/ADSP-21062L t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SHBGI t SBRI t HRPBAI t TRDYHG t HBGRCSV t TRCPA ...
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... WR goes low after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces- HBGRCSV sor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition. CLKIN REDY (O/D) REDY (A/D) drive the RD and WR pins to access the ADSP-21062’ ...
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... REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL t WWRL t SDATWH t t DRDYWRL RDYPWR ADSP-21062/ADSP-21062L t HADRDH t WRWH t HDARWH t DRDHRDY t t HADWRH SADWRH t HCSWRH t WRWH t HDATWH t DWRHRDY ...
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... DT STSCK t HTSCK t t MIENS, MIENHG t DATEN t ACKEN t MENHBG ADSP-21062L Min Max DT/2 –1.25 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT 5DT/16 –0.5 – DT/8 7 – DT/8 7.5 + DT/4 –1 – DT/8 6 – ...
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... DT DT 3DT 5DT/8 –2 – DT/8 6 – DT 9DT/ –0. 5DT DT/ DT/ 9DT/ 3DT –0 ADSP-21062/ADSP-21062L , and ACK 3-0 , RD, WR, 31-0 ADSP-21062L Min Max 5DT 7DT 7DT DT DT 3DT 5DT/8 –2 – DT/8 6 – DT 9DT/ –0. 5DT DT/ DT/ 9DT/ 3DT – 9DT/ × ...
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... ADSP-21062/ADSP-21062L CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ...
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... Only required for interrupt recognition in the current cycle. ADSP-21062/ADSP-21062L ADSP-21062 Min Max DT/2 28.5 + DT/2 1 – DT DT/2 18 –7 15.5 2.5 –3 (t /2) – / /2) – 1. × /2) + 8. ADSP-21062L Min Max Units DT/2 28.5 + DT/2 ns – DT DT –7 ns 15.5 ns 2.5 ns – /2) – / /2) – 1 ...
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... The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21062 Setup Skew LCLKTWH ADSP-21062 Hold Skew ADSP-21062L Setup Skew = 2.10 ns max ADSP-21062L Hold Skew = 1.87 ns max ADSP-21062 Min Max 2.5 2.25 t ...
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... LINK PORT ENABLE OR THREE-STATE TAKES EFFECT TWO CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER. LINK PORT INTERRUPT SETUP TIME CLKIN t HLCK t SLCK LCLK LACK LAST NIBBLE FIRST NIBBLE TRANSMITTED TRANSMITTED t t SLACH HLACH t LCLKIW t LCLKRWL t HLDCL IN t TDLK ADSP-21062/ADSP-21062L LCLK INACTIVE (HIGH) t DLACLK t DLALC ...
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... SCLK width. ADSP-21062 Min Max 4.5 –1 /2) – 2.5 (t /2) + 2.5 SCLK SCLK 3 4. 3DT 12.75 3.5 ADSP-21062L Min Max Units 3 1 4.5 ns –1 /2) – 2.5 (t /2) + 2.5 ns SCLK SCLK 7.5 ...
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... TCLK / RCLK TCLK / RCLK CLKIN SPORT ENABLE AND THREE-STATE LATENCY TFS (EXT) IS TWO CYCLES NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING. ADSP-21062/ADSP-21062L DRIVE SAMPLE EDGE EDGE t SCLKW t DFSE t HOFSE ...
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... ADSP-21062/ADSP-21062L RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT EXTERNAL RFS with MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t (SEE NOTE 2 HOFSE/I ON PREVIOUS PAGE) t SFSE/I t DDTE DDTENFS HDTE/I 1ST BIT t DDTLFSE DRIVE DRIVE SAMPLE t (SEE NOTE 2 HOFSE/I ON PREVIOUS PAGE) t SFSE/I t DDTE DDTENFS HDTE/I 1ST BIT ...
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... Min Max 18.5 , LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 3-0 , LxCLK, LxACK, BMS. 3-0 t TCK t t STAP HTAP t DTDO t SSYS t DSYS ADSP-21062/ADSP-21062L ADSP-21062L Min Max Units 18 18 RPBA, IRQ , ID , FLAG , DR0, DR1, 6-1 2-0 2-0 3-0 , CPA, FLAG , TIMEXP, DT0, ...
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... ADSP-21062/ADSP-21062L OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21062. The curves represent the current drive capability of the output drivers as a function of output voltage. POWER DISSIPATION Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers ...
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... To determine the data output hold time in a particular system, using the equation given above. Choose ∆V first calculate t DECAY to be the difference between the ADSP-21062’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0 the total bus capacitance (per ...
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... ADSP-21062/ADSP-21062L 100 5.25V, – ° 5.0V, +25 C –25 –50 ° 4.75V, +85 C –75 –100 5.0V, +25 –125 –150 –175 –200 0 0.75 1.50 2.25 3.00 SOURCE VOLTAGE – V 16.0 14.0 12.0 RISE TIME 10 0.005X + 3.7 8.0 FALL TIME 6.0 4.0 2 0.0031X + 1 100 120 LOAD CAPACITANCE – ...
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... LOAD CAPACITANCE – pF ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP-21062 is available in 240-lead thermally enhanced MQFP and 225-lead plastic ball grid array packages. The top surface of the thermally enhanced MQFP contains a copper slug from which most of the die heat is dissipated. The slug is flush with the top surface of the package ...
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... ADSP-21062/ADSP-21062L 225-Ball Plastic Ball Grid Array (PBGA) Package Descriptions Ball # Name Ball # Name BMS A01 D01 ADDR25 A02 ADDR30 D02 ADDR26 DMAR2 MS2 A03 D03 A04 DT1 D04 ADDR29 DMAR1 A05 RCLK1 D05 A06 TCLK0 D06 TFS1 CPA A07 RCLK0 D07 ...
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... GND DATA6 DATA5 DATA2 L0DAT0 L1DAT1 L2DAT3 DATA3 DATA1 L0DAT3 L1DAT3 L1ACK L2DAT0 DATA0 L0DAT1 L0ACK L1DAT0 L2DAT2 L2CLK L0DAT2 L0CLK L1DAT2 L1CLK L2DAT1 L2ACK ADSP-21062/ADSP-21062L ADRCLK RCLK0 TCLK0 RCLK1 DT1 HBR RD REDY DR0 DT0 DR1 SBTS WR RFS0 TFS0 RFS1 TCLK1 ...
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... ADSP-21062/ADSP-21062L 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.101 (2.57) 0.091 (2.32) 0.081 (2.06) NOTES 1.THE ACTUAL POSITION OF THE BALL ARRAY IS WITHIN 0.12 (0.30) OF ITS IDEAL POSITION RELATIVE TO THE EDGE OF THE PACKAGE. 2.THE ACTUAL POSITION OF ANY BALL IS WITHIN 0.004 (0.10) OF ITS IDEAL POSITION RELATIVE TO THE ARRAY OF BALLS. ...
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... VDD 156 GND 117 DATA44 157 DATA17 118 DATA43 158 DATA16 119 DATA42 159 DATA15 120 GND 160 VDD ADSP-21062/ADSP-21062L 180 121 Pin Pin Pin Pin No. Name No. Name 201 L2DAT0 161 DATA14 162 DATA13 202 L2CLK 203 L2ACK 163 DATA12 204 NC ...
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... ADSP-21062KS-160 0°C to +85°C ADSP-21062KB-160 0°C to +85°C ADSP-21062CS-160 –40°C to +100°C ADSP-21062LKS-133 0°C to +85°C ADSP-21062LKS-160 0°C to +85°C ADSP-21062LKB-160 0°C to +85°C ADSP-21062LAB-160 –40°C to +85°C ADSP-21062LCS-160 –40°C to +100°C OUTLINE DIMENSIONS Dimensions shown in inches and (mm). ...