GAL18V10 Lattice Semiconductor Corp., GAL18V10 Datasheet

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GAL18V10

Manufacturer Part Number
GAL18V10
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• LOW POWER CMOS
• ACTIVE PULL-UPS ON ALL PINS
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
18v10_04
Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 75 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
2
) floating gate technology to provide a very flexible 20-pin
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
technol-
1
Functional Block Diagram
Pin Configuration
I
I
I
I
I
4
6
8
I/CLK
I/O/Q
I
9
I
I
I
I
I
I
I
GAL18V10
GND
2
I
PLCC
Top View
I/CLK
I/O/Q
11
High Performance E
I/O/Q I/O/Q
Vcc
20
I/O/Q
13
18
16
14
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL18V10
RESET
PRESET
10
10
8
8
8
8
8
8
8
8
I/CLK
I/O/Q
GND
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
November 2003
1
10
5
18V10
2
DIP
GAL
CMOS PLD
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
20
15
11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

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GAL18V10 Summary of contents

Page 1

... The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC configured by the user. The GAL18V10 OLMC is fully com- patible with the OLMC in standard bipolar and CMOS 22V10 de- vices. ...

Page 2

... GAL18V10 Ordering Information Commercial Grade Specifications Part Number Description GAL18V10B Device Name Speed (ns Low Power Power ...

Page 3

... This allows each output to be individually configured as either active high or active low. Output Logic Macrocell Configurations Each of the Macrocells of the GAL18V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler ...

Page 4

... Registered Mode ACTIVE LOW Combinatorial Mode ACTIVE LOW Specifications GAL18V10 ACTIVE HIGH ACTIVE HIGH ...

Page 5

... GAL18V10 Logic Diagram/JEDEC Fuse Map 0000 0036 . . . 0324 0360 . . . 0648 2 0684 . . . 0972 3 1008 . . . 1296 4 1332 . . . . 1692 5 1728 . . . . 2088 6 2124 . . . 2412 7 2448 . . . 2736 8 2772 . . . 3060 3096 . . . 3384 3420 3476, 3477 ... Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte ...

Page 6

... The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL18V10B Recommended Operating Conditions (1) Commercial Devices: +1 ...

Page 7

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Capacitance (T = 25° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL18V10B Over Recommended Operating Conditions COM -7 MIN. MAX. — 7.5 — 5.5 — 3.5 5.5 — 0 — ...

Page 8

... Clock Width INPUT or I/O FEEDB ACK DRIVI CLK Synchronous Preset Specifications GAL18V10 INPUT or I/O FEEDB ACK VALID INPUT ...

Page 9

... 390Ω 50pF 390Ω 50pF 390Ω 50pF 390Ω 5pF 390Ω 5pF 9 Specifications GAL18V10 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ Note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu) ...

Page 10

... The signature data is always available to the user independent of the state of the security cell. Security Cell A security cell is provided in every GAL18V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device ...

Page 11

... OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Circuitry within the GAL18V10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins ...

Page 12

... GAL18V10B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0 Number of Outputs Switching Delta Tpd vs Output Loading ...

Page 13

... GAL18V10B: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.75 0.5 0. Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vin (V) Voh vs Ioh Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 5.50 -55 - Temperature (deg. C) ...

Page 14

... GAL18V10B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs. Vcc 1.3 1.2 1.1 1 0.9 0 -> -> H 0.7 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd vs. Temperature 1.3 1.2 1.1 1 0.9 0.8 0.7 -50 - 100 Ambient Temperature (°C) Delta Tpd vs Outputs Switching Max Max Outputs I vs 250 200 150 ...

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