IFX 80471SK V50 Infineon Technologies, IFX 80471SK V50 Datasheet - Page 20

• Manufacturer Part Number: IFX 80471SK V50
• Manufacturer: Infineon Technologies

Specifications of IFX 80471SK V50

• Packages: PG-DSO-14
• Comment: Vin up to 60V; external MOS; PG-DSO-14
• Vq (max): 5.0 V
• Iq (max): 2,300.0 mA
• Iq (typ): 130.0 µA
• Output: Buck Converter

6
In the following, the internal blocks of the IFX80471 are described in more detail. For selecting external
components please refer to the section
6.1
To meet also high requirements in terms of current consumption a special PFM (Pulse Frequency Modulation) -
PWM (Pulse Width Modulation) control scheme for highest efficiency is implemented in the IFX80471 regulators.
Under light load conditions the output voltage is able to increase slightly and at a certain threshold the controller
jumps into PFM mode. In this PFM operation the PMOS is triggered with a certain on time (depending on input
voltage, output voltage, inductance- and sense resistor value) whenever the buck output voltage decreases to the
so called WAKE-threshold. The switching frequency of the step down regulator is determined in the PFM mode by
the load current. It increases with increasing load current and turns finally to the fixed PWM frequency at a certain
load current depending on the input voltage, current sense resistor and inductance. The diagram below shows the
buck regulation circuit of the IFX80471.
Figure 3
The IFX80471 uses a slope-compensated peak current mode PWM control scheme in which the feedback or
output voltage of the step down circuit and the peak current of the current through the PMOS are compared to
form the OFF signal for the external PMOS. The ON-trigger is set periodically by the internal oscillator when acting
in PWM mode and is given by the output of the WAKE-comparator when operating in PFM mode. The Multiplexer
(MUX) is switched by the output of the MODE-detector which distinguishes between PFM and PWM by tracking
the output voltage (go to PFM) and by tracking the gate trigger frequency (goto PWM). In PFM mode the peak
current limit is reduced to prevent overshoots at the output of the buck regulator. In order to avoid a gate turn off
signal due to the current peak caused by the parasitic capacitance of the catch diode the blanking filter is
necessary. The blanking time is set internally to 200ns and determines (together with the PMOS turn on and turn
off delay) the minimum duty cycle of the device. In addition to the PFM/PWM regulation scheme an overvoltage
lockout and thermal protection are implemented to guarantee safe operation of the device and of the supplied
application circuit.
Data Sheet
VREF
VFB
+
-
Detailed Circuit Description
PFM/PWM Step-down regulator
Buck control scheme
Amplifier
compensation
Error
Slope-
VS
+
+
-
CS
Amplifier
Current-
sense
VFB, WK
SYNC
VREF
“Application Information” on Page
Comparator
PWM
Oscillator
-
Blanking
Comparator
VFB, OV
Wake-
+
19
-
VREF
PFM
PWM
Lockout
MUX
MODE
Voltage
Over-
>1
VREF
R
S
Q
+
21.
-
VDIODE
Shutdown
&
Detailed Circuit Description
Temp.
Over-
Level-
shift
Rev. 1.0, 2011-02-07
BDS
VS
IFX80471
GDRV