BTS 5682E Infineon Technologies, BTS 5682E Datasheet - Page 37

• Manufacturer Part Number: BTS 5682E
• Manufacturer: Infineon Technologies

Specifications of BTS 5682E

• Packages: PG-DSO-36
• Channels: 6.0
• Channel Mix: 3x50mohm+2*130mohm+1*230mohm
• Led Mode: Yes
• Cranking Mode: Yes
• Pwm Engine Integrated: No

9
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter
ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain
capability.
Figure 19
9.1
CS - Chip Select:
The system micro controller selects the SPOC - BTS5682E by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
•
•
CS Low to High transition:
•
•
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
further information.
Data Sheet
The requested information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
Data from shift register is transferred into the addressed register.
Serial Peripheral Interface (SPI)
Serial Peripheral Interface
SPI Signal Description
SCLK
SO
CS
time
SI
CS
MSB
MSB
6
6
5
5
4
4
3
3
37
2
2
1
1
LSB
LSB
Serial Peripheral Interface (SPI)
SPOC - BTS5682E
SPI.emf
Rev. 1.0, 2008-01-22
Section 9.5
for