IR3500VMPBF International Rectifier, IR3500VMPBF Datasheet - Page 24

• Manufacturer Part Number: IR3500VMPBF
• Description: The IR3500V Control IC combined with one or more xPhase3 Phase IC implement the control and MOSFET driver functions for a VR11.1 CPU VTT power supply.
• Manufacturer: International Rectifier

Specifications of IR3500VMPBF

• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available

APPLICATIONS INFORMATION
DESIGN PROCEDURE
Oscillator Resistor Rosc
The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
each phase converter equals the PHSOUT frequency, which is set by the external resistor R
curve in Figure 23. The CLKOUT frequency equals the switching frequency multiplied by the phase number. The
Rosc sets the reference current used for the no load offset and OCSET which is given by Figure 5 and equals:
Soft Start Capacitor C
The soft start capacitor C
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 12. After the
ENABLE pin voltage rises above 0.85V, there is a soft-start delay time TD1
is released to allow the soft start of output voltage. The soft start time TD2 represents the time during which
converter voltage rises from zero to 1.1V
boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID changes from boot voltage to the final
voltage. The VR ready delay time (TD5) is the time period from VR reaching the final voltage to the VR ready
signal being issued, which is determined by the delay comparator threshold.
C
SS/DEL
ROSC/OVP
Error Amp
& IIN drive
Discharge
OV clears
high until
Disabled
Clearing
SS/DEL
Method
PGood
Delay?
Flags
Fault
Page 24 of 34
= 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
Open
Daisy
32 Clock
Pulses
SS/DEL
TD
PHSOUT
Control
Pulses
SS/DEL
Open
Loop
No
1
8
=
Recycle VCCL
C
SS
programs five different time parameters. They include soft start delay time, soft
ISETPT
/
I
DEL
Sense
CHG
Open
Line
No
1 *
4 .
.
=
The VID sample delay time (TD3) is the time period when VID stays at
IOCSET
=
Voltage
Over
C
Yes
No
Figure 20 – Fault Table
52
SS
5 .
/
DEL
*
=
10
1.3us
Blank
Time
1 *
. 0
VID
Rosc
−
6
595
4 .
Yes
Yes
Fault Type
Disable
250 ns
Blank
Time
Yes
Resume Normal Operation when Condition Clears
VCCL
UVLO
No
,
after which the error amplifier output
(1)
Programmed by
Pulses. Count
ROSC value
OC Before
PHSOUT
Start-up
No
(2)
July 28, 2008
OSC
Discharge
Threshold
OC After
Start-up
SS/DEL
IR3500V
according to the
VOUT
UVLO
No
No
No