IR3500VMPBF International Rectifier, IR3500VMPBF Datasheet - Page 18

• Manufacturer Part Number: IR3500VMPBF
• Description: The IR3500V Control IC combined with one or more xPhase3 Phase IC implement the control and MOSFET driver functions for a VR11.1 CPU VTT power supply.
• Manufacturer: International Rectifier

Specifications of IR3500VMPBF

• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available

IR3500V
Linear Regulator Output (VCCL)
The IR3500V has a built-in linear regulator controller, and only an external NPN transistor is needed to create a
linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the
resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs
along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The
linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. Due to stability reasons, there is an
upper limit to the maximum value of capacitor that can be used at this pin and it’s a function of the number of
phases used in the multiphase architecture and their switching frequency. Figure 14 provides Bode plots for the
linear regulator with 5 phases switching at 750 kHz.
Figure 14 - VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz.
VCCL Under Voltage Lockout (UVLO)
The IR3500V has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage
instead, which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up,
the fault latch will be reset if VCCL is above 94% of the voltage set by resistor divider at VCCLFB pin. If VCCL
voltage drops below 86% of the set value, the fault latch will be set.
VID Fault Codes
VID codes of 0000000X and 1111111X will set the fault latch and disable the error amplifier. A 1.3us delay is
provided to prevent a fault condition from occurring during Dynamic VID changes. A VID FAULT condition is latched
and can only be cleared by cycling power to VCCL.
Voltage Regulator Ready (PGOOD)
The PGOOD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
start-up, it is pulled low with an input voltage as low as 2 V. Until the soft start cycle is complete, PGOOD remains
low until the output voltage is within regulation and SS/DEL is above 3.92V. The PGOOD pin drives low if the fault
latch, over voltage latch, open sense line latch, or open daisy chain latch is set. A high level at the PGOOD pin
indicates that the converter is in operation and has no fault. The PGOOD stays high as long as the output voltage is
within 300 mV of the programmed VID.
Page 18 of 34
July 28, 2008