HCPL316J500E AVAGO TECH, HCPL316J500E Datasheet - Page 11

• Manufacturer Part Number: HCPL316J500E
• Manufacturer: AVAGO TECH

Notes:
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once V
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of V
14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of V
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |t
17. As measured from V
18. The difference between t
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before V
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 µs is the guaran-
23. Common mode transient immunity in the high state is the maximum tolerable
24. Common mode transient immunity in the low state is the maximum tolerable dV
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at V
27. The recommended output pull-down resistor between V
28. In most applications V
11
4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detec-
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
5. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (V
tion current limit,
I
lation Characteristic Table, if applicable.
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction tem-
perature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power
dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB
Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C.
Input IC power dissipation does not require derating.
peak minimum = 2.0 A. See Applications section for additional details on I
compensates for increased I
VLO+
will approach V
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection.
teed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications
notes at the end of this data sheet for further details.
dV
a 3K Ω pull-up resistor is needed in fault detection mode.
output will remain in a low state (i.e., V
µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-
down resistor is not used.
of the IGBT gate. In applications where V
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during V
I-O
CM
≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insu-
threshold of 13.5 V. For High Level Output Voltage testing, V
/dt of the common mode pulse, V
OUT
of the HCPL-316J is allowed to go high (V
CC
as I
IN+
OH
CC1
, V
approaches zero units.
PHL
IN-
will be powered up first (before V
OPEAK
to V
and t
OUT
CC
PLH
due to changes in V
.
- 3 V
between any two HCPL-316J parts under the same test conditions.
O
CM
BE
< 1.0 V or FAULT < 0.8 V).
CC2
, a pull-down resistor between the output and V
, to assure that the output will remain in the high state (i.e., V
PHL
is powered up first, it is important to ensure that V
- t
PLH
CC2
| for any given unit.
OL
- V
OUT
over temperature.
E
CC2
> V
and V
) and powered down last (after V
UVLO
OH
EE
CC2
is measured with a dc load current. When driving capacitive loads, V
), the DESAT detection feature of the HCPL-316J will be the primary
does not contribute any output current when V
CC2
- V
CC2
- V
E
OH
.
OUT
E
.
- V
peak. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This
begins to go low, and the FAULT output to go low.
E
) to ensure adequate margin in excess of the maximum V
UVLO+
CM
/dt of the common mode pulse, V
> 11.6 V, DESAT will remain functional until V
EE
is recommended to sink a static current of 650
CC1
in+
CC2
remains low until V
ramp-up or ramp-down.
). This is desirable for maintaining control
O
> 15 V or FAULT > 2 V). A 100 pF and
OUT
CC1
CM
, to assure that the
= V
reaches the proper
EE
.
UVLO-
O
OH
U-
<