TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 124

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

11.3.3 Transfer modes
11.3.2.3 Transmit/receive mode
11.3.3.1 Transmit mode
Transmit, receive and transmit/receive mode are selected by using SIOCR1<SIOM>.
(2)
(1)
(2)
(1)
Transmit mode is selected by writing “00B” to SIOCR1<SIOM>.
received sequentially beginning with the least significant bit (Bit0).
data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received
sequentially beginning with the most significant (Bit7).
data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received
sequentially beginning with the least significant (Bit0).
SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
to “0”.
SCK
SIOCR1<SIODIR>, synchronizing with the
clock falling edge.
ferred to shift register, then the INTSIO interrupt request is generated, synchronizing with the next
falling edge on
LSB receive mode
LSB receive mode is selected by setting SIOCR1<SIODIR> to “1”, in which case the data is
MSB transmit/receive mode
MSB transmit/receive mode are selected by setting SIOCR1<SIODIR> to “0” in which case the
LSB transmit/receive mode
LSB transmit/receive mode are selected by setting SIOCR1<SIODIR> to “1”, in which case the
Starting the transmit operation
Transmit mode is selected by setting “00B” to SIOCR1<SIOM>. Serial clock is selected by using
When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of
The data is transferred sequentially starting from SO pin with the direction of the bit specified by
SIOSR<SEF> is kept in high level, between the first clock falling edge of
SIOSR<TXF> is set to “1” at the rising edge of pin after the data written to the SIOTDB is trans-
Note 1: In internal clock operation, when SIOCR1<SIOS> is set to "1", transfer mode does not start with-
Note 2: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift
Note 3: In external clock operation, when the falling edge is input from
pin.
out writing a transmit data to the transmit buffer register (SIOTDB).
register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
pin.
set to "1", SIOTDB is transferred to shift register immediately.
SCK
pin.
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SCK
pin's falling edge.
SCK
pin after SIOCR1<SIOS> is
SCK
TMP86CS44UG
pin and eighth
SCK