TMP86xy08I/S/DMG/NG Toshiba, TMP86xy08I/S/DMG/NG Datasheet - Page 52

• Manufacturer Part Number: TMP86xy08I/S/DMG/NG
• Manufacturer: Toshiba

Specifications of TMP86xy08I/S/DMG/NG

• Package: SSOP30/SDIP30
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 4/8
• Ram Size: 256/256
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: 6
• Adc 10-bit Channels: -
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

3.6 Undefined Instruction Interrupt (INTUNDEF)
3.7 Address Trap Interrupt (INTATRAP)
3.8 External Interrupts
3.5.2 Debugging
erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-
rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-
cess is broken and INTATRAP interrupt process starts, soon after it is requested.
(Pulse inputs of less than a certain time are eliminated as noise).
interrupt input pin or an input/output port, and is configured as an input port during reset.
control register (EINTCR).
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
The TMP86C808DMG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
Edge selection is also possible with INT1,INT3,INT4. The
Edge selection, noise reject control and
address.
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
(SWI) does.
watchdog timer control register (WDTCR).
INT0
/P10 pin function selection are performed by the external interrupt
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INT0
/P10 pin can be configured as either an external
TMP86C808DMG