TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 52

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Symbol Name Address
Symbol Name Address
INTCLR
IIMC
INT0 level enable
0
1
Interrupt
input
mode
control
Interrupt
clear
control
edge detect INT
High level INT
(2) External interrupt control
(3) Interrupt request flag clear register
(4) Micro DMA start vector registers
(Prohibit
(Prohibit
vector, to the register INTCLR.
operation after execution of the DI instruction.
source with a micro DMA start vector that matches the vector set in this register is
assigned as the micro DMA start source.
end interrupt corresponding to the channel is sent to the interrupt controller, the micro
DMA start vector register is cleared, and the micro DMA start source for the channel is
cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector
register again during the processing of the micro DMA transfer end interrupt.
channel, the channel with the lowest number has a higher priority.
channels, the interrupt generated in the channel with the lower number is executed
until micro DMA transfer is complete. If the micro DMA start vector for this channel is
not set again, the next micro DMA is started for the channel with the higher number.
(Micro DMA chaining.)
RMW)
RMW)
8CH
88H
The interrupt request flag is cleared by writing the appropriate micro DMA start
For example, to clear the interrupt flag INT0, perform the following register
INTCLR ← 0AH: Clears interrupt request flag INT0.
This register assigns micro DMA processing to which interrupt source. The interrupt
When the micro DMA transfer counter value reaches zero, the micro DMA transfer
If the same vector is set in the micro DMA start vector registers of more than one
Accordingly, if the same vector is set in the micro DMA start vector registers of two
Always
write 0.
7
−
0
7
Always
write 0.
6
−
0
6
INT3EDGE
0: Rising
1: Falling
I3EDGE
91C025-50
CLRV5
5
0
5
0
INT2EDGE
0: Rising
1: Falling
I2EDGE
CLRV4
4
0
4
0
W
INT1EDGE
0: Rising
1: Falling
I1EDGE
CLRV3
3
0
Interrupt Vector
3
0
W
INT0EDGE
0: Rising
1: Falling
I0EDGE
CLRV2
2
0
2
0
INT0 mode
0: Edge
1: Level
CLRV1
I0LE
1
0
1
0
TMP91C025
2007-02-28
Always
write 0.
CLRV0
0
0
0
−
0