74HC125DTR2G ON Semiconductor, 74HC125DTR2G Datasheet
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74HC125DTR2G
Specifications of 74HC125DTR2G
Related parts for 74HC125DTR2G
74HC125DTR2G Summary of contents
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Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is ...
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... SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). LOGIC DIAGRAM Active−Low Output Enables ...
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... OL Voltage I Maximum Input Leakage Current in I Maximum Three−State Leakage OZ Current I Maximum Quiescent Supply Current CC (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Min Max 2.0 6 – 125 1000 ...
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... Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D). ORDERING INFORMATION Device 74HC125DR2G 74HC125DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. (C ...
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INPUT A 50% 10% t PLH OUTPUT Y 90% 50% 10% t TLH Figure 1. TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 3. Test Circuit OE A SWITCHING WAVEFORMS OE (HC125A) ...
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... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...
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... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...