74LV125N,112 NXP Semiconductors, 74LV125N,112 Datasheet - Page 2
![IC BUFF DVR TRI-ST QUAD 14PDIP](/photos/6/57/65747/568-14-dip_sot27-1_sml.jpg)
74LV125N,112
Manufacturer Part Number
74LV125N,112
Description
IC BUFF DVR TRI-ST QUAD 14PDIP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet
1.74LV125N112.pdf
(15 pages)
Specifications of 74LV125N,112
Package / Case
14-DIP (0.300", 7.62mm)
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
16mA, 16mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Logic Family
74LV
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
High Level Output Current
- 16 mA
Input Bias Current (max)
160 uA
Low Level Output Current
16 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
9 ns
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2924-5
935063160112
935063160112
NXP Semiconductors
4. Functional diagram
5. Pinning information
74LV125_3
Product data sheet
Fig 1.
Fig 4.
Logic symbol
Pin configuration DIP14, SO14
10
12
13
2
1
5
4
9
1OE
2OE
3OE
4OE
1A
2A
3A
4A
GND
1OE
2OE
1A
1Y
2A
2Y
5.1 Pinning
mna228
1
2
3
4
5
6
7
1Y
2Y
3Y
4Y
74LV125
11
3
6
8
001aaj961
14
13
12
11
10
9
8
V
4OE
4A
4Y
3OE
3A
3Y
Fig 2.
CC
Rev. 03 — 7 April 2009
IEC logic symbol
10
12
13
2
1
5
4
9
EN1
mna229
1
Fig 5.
11
3
6
8
Pin configuration SSOP14, TSSOP14
GND
1OE
2OE
1A
1Y
2A
2Y
1
2
3
4
5
6
7
Fig 3.
nOE
nA
Quad buffer/line driver; 3-state
74LV125
Logic diagram (one buffer)
001aaj921
© NXP B.V. 2009. All rights reserved.
14
13
12
11
10
74LV125
9
8
V
4OE
4A
4Y
3OE
3A
3Y
CC
mna227
2 of 15
nY