74AUP1G17GW,125 NXP Semiconductors, 74AUP1G17GW,125 Datasheet - Page 9

IC BUFF SCHMT TRG LOW PWR 5TSSOP

74AUP1G17GW,125

Manufacturer Part Number
74AUP1G17GW,125
Description
IC BUFF SCHMT TRG LOW PWR 5TSSOP
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP1G17GW,125

Package / Case
SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Logic Type
Schmitt Trigger - Buffer, Driver
Number Of Elements
1
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Number Of Channels Per Chip
1
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
0.5 uA
Low Level Output Current
4 mA
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Output Current
20 mA
Output Voltage
4.6 V
Propagation Delay Time
19 ns @ 1.1 V to 1.3 V or 11.2 ns @ 1.4 V to 1.6 V or 9.2 ns @ 1.65 V to 1.95 V or 7 ns @ 2.3 V to 2.7 V or 6.2 ns @ 3 V to 3.6 V
Number Of Lines (input / Output)
1 / 1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2561-2
935279024125
NXP Semiconductors
12. Waveforms
Table 9.
Table 10.
[1]
74AUP1G17
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Supply voltage
V
0.8 V to 3.6 V
Fig 7.
Fig 8.
CC
CC
For measuring enable and disable times R
Measurement points are given in
Logic levels: V
The data input (A) to output (Y) propagation delays
Test data is given in
Definitions for test circuit:
R
C
R
V
Test circuit for measuring switching times
L
L
T
EXT
Measurement points
Test data
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to the output impedance Z
= External voltage for measuring switching times.
Load
C
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
OL
L
and V
Table
Output
V
0.5  V
OH
M
10.
are typical output voltage levels that occur with the output load.
Y output
CC
A input
Table
L
All information provided in this document is subject to legal disclaimers.
G
= 5 k, for measuring propagation delays, setup and hold times and pulse width R
GND
9.
V
V
OH
OL
V
I
V I
Rev. 4 — 15 July 2010
R
Input
V
0.5  V
L
R T
M
[1]
V
M
DUT
V
V
CC
CC
M
t
PHL
V O
V
t
open
PLH
C L
EXT
o
001aac521
of the pulse generator.
V
, t
EXT
V
V
PHL
I
CC
5 kΩ
R L
mnb153
t
PLH
t
GND
PZH
Low-power Schmitt trigger
, t
74AUP1G17
PHZ
t
 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
f
t
2  V
PZL
, t
CC
PLZ
L
= 1 M.
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