LM1882CM National Semiconductor, LM1882CM Datasheet - Page 6

• Manufacturer Part Number: LM1882CM
• Description: IC PROGRAM VIDEO SYNC GEN SO20
• Manufacturer: National Semiconductor
• Type: Video Syncr

Specifications of LM1882CM

• Applications: Monitors, TV
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LM1882CM

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Addressing Logic
LOAD will load the first byte of data. Auto Incrementing is
disabled on the falling edge of LOAD after ADDRDATA and
LHBYTE goes low.
Manual Addressing Mode
Auto Addressing Mode
ADDRDEC LOGIC
The ADDRDEC logic decodes the current address and gen-
erates the enable signal for the appropriate register. The en-
able values for the registers and counters change on the fall-
ing edge of LOAD. Two types of ADDRDEC logic is enabled
by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-
start logic) and Addresses 23 or 55 (Vectored Clear logic).
Loading these addresses will enable the appropriate logic
and put the part into either a Restart (all counter registers are
reinitialized with preprogrammed data) or Clear (all registers
are cleared to zero) state. Reloading the same ADDRDEC
address will not cause any change in the state of the part.
The outputs during these states are frozen and the internal
Cycle #
1
2
3
4
5
6
Cycle #
1
2
3
4
5
6
(Continued)
Enable Auto Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Load Falling Edge
Load Falling Edge
6
CLOCK is disabled. Clocking the part during a Vectored Re-
start or Vectored Clear state will have no effect on the part.
To resume operation in the new state, or disable the Vec-
tored
non-ADDRDEC address must be loaded. Operation will be-
gin in the new state on the rising edge of the non-ADDRDEC
load pulse. It is recommended that an unused address be
loaded following an ADDRDEC operation to prevent data
registers from accidentally being corrupted. The following
Addresses are used by the device.
Address 0
Address 1–18Data Registers REG1–REG18
Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n+1)
Load Hbyte (n+1); Inc Counter
Load Address
Restart
Load Address m
Load Lbyte m
Load Hbyte m
Load Address n
Load Lbyte n
Load Hbyte n
Load Rising Edge
Status Register REG0
Load Rising Edge
or
Vectored
Clear
DS100232-7
DS100232-8
state,
another