LM1882CM National Semiconductor, LM1882CM Datasheet

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LM1882CM

Manufacturer Part Number
LM1882CM
Description
IC PROGRAM VIDEO SYNC GEN SO20
Manufacturer
National Semiconductor
Type
Video Syncr
Datasheet

Specifications of LM1882CM

Applications
Monitors, TV
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*LM1882CM
© 1998 National Semiconductor Corporation
LM1882 • 54ACT715
LM1882-R • 54ACT715-R Programmable Video Sync
Generator
General Description
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin
TTL-input compatible devices capable of generating Hori-
zontal, Vertical and Composite Sync and Blank signals for
televisions and monitors. All pulse widths are completely de-
finable by the user. The devices are capable of generating
signals for both interlaced and noninterlaced modes of op-
eration. Equalization and serration pulses can be introduced
into the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system
architecture. Line rate and field/frame rate are all a function
of the values programmed into the data registers, the status
register, and the input clock frequency.
The ’ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming be-
fore operation.
The ’ACT715-R/LM1882-R is the same as the ’ACT715/
LM1882 in all respects except that the ’ACT715-R/
Connection Diagrams
TRI-STATE
FACT
is a trademark of Fairchild Semiconductor Corporation.
®
Order Number LM1882CN or LM1882CM
is a registered trademark of National Semiconductor Corporation.
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM
Pin Assignment for
DIP and SOIC
DS100232
DS100232-1
LM1882-R is mask programmed to default to a Clock En-
abled state. Bit 10 of the Status Register defaults to a logic
“1”. Although completely (re)programmable, the ’ACT715-R/
LM1882-R version is better suited for applications using the
default 14.31818 MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
Features
n Maximum Input Clock Frequency
n Interlaced and non-interlaced formats available
n Separate or composite horizontal and vertical Sync and
n Complete control of pulse width via register
n All inputs are TTL compatible
n 8 mA drive on all outputs
n Default RS170/NTSC values mask programmed into
n 4 KV minimum ESD immunity
n ’ACT715-R/LM1882-R is mask programmed to default to
Blank signals available
registers
a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
programming
Pin Assignment
for LCC
>
130 MHz
December 1998
DS100232-2
www.national.com

Related parts for LM1882CM

LM1882CM Summary of contents

Page 1

... The ’ACT715-R/LM1882-R is the same as the ’ACT715/ LM1882 in all respects except that the ’ACT715-R/ Connection Diagrams Pin Assignment for DIP and SOIC DS100232-1 Order Number LM1882CN or LM1882CM For Default RS-170, Order Number LM1882-RCN or LM1882-RCM TRI-STATE ® registered trademark of National Semiconductor Corporation. FACT ™ ...

Page 2

Logic Block Diagram Pin Description There are a Total of 13 inputs and 5 outputs on the ’ACT715/ LM1882. Data Inputs D0–D7: The Data Input pins connect to the Ad- dress Register and the Data Input Register. ADDR/DATA: The ADDR/DATA ...

Page 3

Register Description (Continued) Bits 0– VCBLANK VCSYNC HBLHDR HSYNVDR CBLANK CSYNC HGATE (DEFAULT VBLANK CSYNC HBLANK CBLANK VSYNC HGATE VBLANK VSYNC HBLANK ...

Page 4

Signal Specification (Continued) posed because during interlace operation this value is inter- nally divided order to generate serration and equal- FIGURE 1. Horizontal Waveform Specification = Horizontal Period (HPER) REG(4) x ckper = [REG(3) − ...

Page 5

Signal Specification (Continued) FIGURE 2. Vertical Waveform Specification FIGURE 3. Equalization/Serration Interval Programming HORIZONTAL AND VERTICAL GATING SIGNALS Horizontal Drive and Vertical Drive outputs can be utilized as general purpose Gating Signals. Horizontal and Vertical Gat- ing Signals are available ...

Page 6

Addressing Logic (Continued) LOAD will load the first byte of data. Auto Incrementing is disabled on the falling edge of LOAD after ADDRDATA and LHBYTE goes low. Manual Addressing Mode Cycle # Auto Addressing ...

Page 7

Addressing Logic (Continued) Address 19–21Unused Address 22/54Restart Vector (Restarts Device) Address 23/55Clear Vector (Zeros All Registers) Address 24–31Unused Address 32–50Register Scan Addresses Address 51–53Counter Scan Addresses Address 56–63Unused At any given time only one register at most is selected. It ...

Page 8

RS170 Default Register Values Reg D Value H Register Description REG0 0 000 Status Register (715/LM1882) REG0 1024 400 Status Register (715-R/LM1882-R) REG1 23 017 HFP End Time REG2 91 05B HSYNC Pulse End Time REG3 157 09D HBLANK Pulse ...

Page 9

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Diode Current ( −0. +0. Input Voltage (V ) −0. Output Diode Current ( −0. +0. Output Voltage (V ) −0. Output Source or Sink Current ( Ground Current ...

Page 10

AC Electrical Characteristics V CC Symbol Parameter (V) f Interlaced f 5.0 MAXI MAX (HMAX/2 is ODD) f Non-Interlaced f 5.0 MAX MAX (HMAX/2 is EVEN) t Clock to Any Output 5.0 PLH1 t PHL1 t Clock to ODDEVEN 5.0 ...

Page 11

Capacitance (Continued) Additional Applications Information POWERING UP The ’ACT715/LM1882 default value for Bit 10 of the Status Register is 0. This means that when the CLEAR pulse is ap- plied and the registers are initialized by loading the default values ...

Page 12

Additional Applications Information FIGURE 6. Default RS170 Hardwire Configuration Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND Components R1: 4.7k C1: 10 µF R2:10k C2 FIGURE 7. ...

Page 13

13 ...

Page 14

Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) www.national.com NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 14 ...

Page 15

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Integrated Circuit (S) 20-Lead Plastic Dual-In-Line Package (P) NS Package Number M20B NS Package Number N20B 15 www.national.com ...

Page 16

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 ...

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