STV2050A STMicroelectronics, STV2050A Datasheet

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... different data sets Self-controlled power-on sequence Figure 1. Functional Block Diagram Frame H/V and Sync Line Timebase I²C Control September 2003 Package: PQFP80 Power Supply: 3.3 V Tape and Reel: STV2050ATR Horizontal and RAM Vertical Defection Corrections Security Control Focus Pattern EEPROM Interface ...

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GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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DATA TRANSFER BETWEEN RAM AND EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 MASTER CLOCK FREQUENCY ...

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... STV2050A - 10.2 FOCUS OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 ELECTRICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 PRINCIPLE OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 LOOP PARAMETER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 LOOP STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 OPERATION OF THE ELECTRICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5 OUTPUT/INPUT PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5.1PORA, PORB and PORC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.5.2OGAH and OGAV Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12 OPTICAL LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.1 PRINCIPAL OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12 ...

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... INDEX OF I²C BUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 STV2050A - 5/83 2 ...

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... STV2050A - GENERAL OVERVIEW 1 GENERAL OVERVIEW 1.1 SYSTEM BLOCK DIAGRAM Figure 2. TV Set Convergence System Diagram Tuner Convergence Application Circuit EEPROM(s) To/From Microprocessor I²C Bus 6/83 IF Video Power Stage GND GND GND R G Focus B Amplifier GND Focus 1 x Sound H/V Deflection ...

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... DEVICE BLOCK DIAGRAM Figure 3. STV2050A Block Diagram TBU7 TBU6 TBU5 TBU4 TBU3 TBU2 TBU1 TBU0 VBLK MLIN OPTI OPTT POUT PORA PORB PORC A VIDB D A VIDG D A VIDR D STV2050A - GENERAL OVERVIEW PLL Logic GNDP VCCP VCCA GNDA VCCG GNDG VCCH ...

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... STV2050A - GENERAL OVERVIEW 1.3 APPLICATION CIRCUIT An application circuit with 2nd EEPROM, Electrical Offset and Gain Adjustment Loop and Op- tical Sensors is shown in the following figure. Figure 4. Application Circuit 3.3 V I²C Bus to µP DATA 3.3 V 3.3 V CLK 3 Video H 3.3 V 3.3 V ...

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... TBU7 X 34 TBU6 X 35 TBU5 X 36 TBU4 X STV2050A - GENERAL OVERVIEW HZ = High Impedance "1" = High Level Output Reset Status and Remarks Master Bus: "Data" Master Bus: "Clock" Digital Supply: Ground Digital Supply: Ground Core / RAM Digital Supply: 3.3 V Core / Digital Supply: 3.3 V Slave Bus: " ...

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... STV2050A - GENERAL OVERVIEW Pin No. Pin Name 37 TBU3 X 38 TBU2 X 39 TBU1 X 40 TBU0 X 41 GNDH 42 VCCH 43 GNDG 44 VCCG 45 DNBH HZ 46 DABH HZ 47 GNDA 48 DNGH HZ 49 DAGH HZ 50 VCCA HZ 51 DNRH HZ 52 DARH HZ 53 GNDI Reference Current 54 REFN Code 0(hex) 55 REFC X 56 ...

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... ECLK GNDN 15 VIDR VIDG VIDB VCCD GNDD 20 OSCL GRES GNDF FILT 24 25 STV2050A - GENERAL OVERVIEW Reset Status and Remarks Protection Pin Control Normally used for electrical loop feedback detec- tion. Can also be set as an inpout or an output PQFP80 30 35 Description 65 DAGV 64 ...

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... TV set is switched off in order to be recovered when switched back on. This data must therefore be stored in EEPROM. The STV2050A has an embedded RAM for storing data used “in real time” high speed. In order to simplify the microcontroller software, and to ensure a quick startup, the STV2050A directly controls one or more ( seven) EEPROMs. The STV2050A has 2 ports for I² ...

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... D0, D1 and D2 as shown in the following figure. The bit order is named as follows: D0[7] is the MSB and D2[0] is the LSB MSB D0 Byte Bit Note: Bit D0[7:6] is not physically implemented in the “Green” and “Blue” banks. STV2050A - STRUCTURE OF THE PROGRAMMING SYSTEM D1 Byte 18.) ...

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... Note: Bits 22 and 23 of the “Red and I²C bank” may be used for general purposes. They are stored to- gether with the convergence data in the external EEPROM. 2.3 ADJUSTMENT DATA SETS The set of data stored at addresses called an ADS (Adjustment Data Set). The STV2050A can store up to three ADSs in one standard EEPROM. Refer to "MASTER I²C BUS INTERFACE" on page 14/83 Green ...

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... ADS0. ADS0 For the address range (RAM), an autoincrement function can be enabled using the AIE (Auto Increment Enable) bit in the E7 register. AIE STV2050A - SLAVE I²C BUS INTERFACE 0 (grounded, internal PLL only 39 (3.3 Volt, external PLL only 3B Autoincrement disabled 1 = Autoincrement enabled ...

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... STV2050A - SLAVE I²C BUS INTERFACE If the autoincrement function is enabled, the internal address is automatically incremented after 3 bytes are either written or read. When the autoincrement counter reaches the CF ad- dress, the counter stops counting and any additional data will be written to or read from the CF address ...

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... When the last byte of the CF address has been transmitted, the IC internal auto-increment ad- dress counter stops counting and the CF value will be read out again. 3.5 I²C I/O LINES Digital filters suppress pulses that are less than clock pulses at the SDAI and SCLS in- puts. STV2050A - SLAVE I²C BUS INTERFACE 17/83 ...

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... Bit D1[3] is the horizontal correction parity bit – Bit D1[2] is the vertical correction parity bit – Bits D1[3:2] are generated by the STV2050A. Their value can be read out only. Note: The STV2050A automatically checks the parity bits of each convergence value before applying them to the DACs ...

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... I²C register content in the EEPROM, the embedded RAM allo- cation is divided into two parts: – From sub-address (included), contents can be stored in the EEPROM, and can then be restored, – From sub-addresses and FE, contents are lost when the STV2050A is switched off and Section 9.1 " ...

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... STV2050A - RAM ALLOCATION 4.2.1 Registers Storable in the EEPROM MSB BYTE RFH[7:0] D1 RFV[7:0] D2 ORH[7:0] D3 ORV[7: BGA[4:0] S S[0 D6 PBH[3:0] PBV[3: HGP[6: HGD[5: VGP[7:0] DA IIE IFA x ICV[5: HDP[6:0] T[8] DC CRH[7:0] DD CRV[7:0] DE FV1[5: FIN RCH[3:0] RCV[3:0] E1 SRH[7:0] E2 SRV[7:0] 20/83 BYTE GFH[7:0] GFV[7:0] OGH[7:0] OGV[7: GAV ...

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... STV2050A code = 30(hex GAV [1: S09 [3:0] S10 [3: S13[7:0] CBS [1:0] MVG[7:0] RWM [2:0] X HAM[3: PAS[4: HG1[3: VG1[3: HG3[3: VG3[3: STV2050A - RAM ALLOCATION BYTE RESERVED 1 9 GAH PIC PIB PIA [1: S12 [3: S14[7: MVB[7: STX[3: HO2[5:0] HG2[3:0] VO2[5:0] VG2[3:0] HO4[5:0] HG4[3:0] VO4[5:0] VG4[3: ...

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... STV2050A - TIMEBASES 5 TIMEBASES 5.1 LINE LOCKED PLL AND SYSTEM CLOCK A frequency-multiplying PLL derives the internal system clock from the incoming signal at the SYNH pin. This signal is derived from horizontal deflection. Figure 9. Line-Locked PLL and System Clock SYNH 100 nF The PLL is designed to drive 1H, 2H, HDTV and SVGA applications. Two loop filters can be implemented using the FILT (pin 24) and FLT2 (pin 25) pads ...

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... The time delay between video position and the output (HGD+ (clk/line) 2 µs from line to line. Greater phase deviations may occur V D (2) ( down up STV2050A - TIMEBASES Section 7.2.1 "Horizontal Grid (HRD+ 23/83 ...

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... Auto-Calibration of DACs All the DACs of the STV2050A can be automatically calibrated. This feature ensures a high matching stability in both time and temperature. The process involves the sequential calibra- tion of 120 cells. To ensure optimal results, each cell must be calibrated at least every 4 ms. ...

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... The autocalibration process is not synchronized to vertical timing 1: The autocalibration is synchronized to vertical IC timing. The counter which selects the DAC cells that are to be calibrated is reset on each frame retrace. STV2050A - TIMEBASES > 8H 25/83 ...

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... The STV2050A can achieve perfect field parity rec- ognition using the “Vertical Sync shifT“ (VST). When the VST[7:0] bits in the DA register are set to the optimum value, the STV2050A distin- guishes perfectly between the two fields. This is used to control the interpolation of the con- vergence values and the video pattern generator according to the interlaced scanning scheme ...

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... Figure 13. Vertical Time Base Vertical Pulse Horizontal Pulses Vertical Grid 1 TV line Number 11 Vertical Convergence Frame Retrace DCB Lines Measurement Line STV2050A - TIMEBASES Register Update DCT Lines MLN Lines 27/83 ...

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... STV2050A - MASTER I²C BUS INTERFACE 6 MASTER I²C BUS INTERFACE A master I²C bus implemented in the STV2050A is used to transfer data between the IC em- bedded RAM and the external 2K x 8-bit EEPROMs (for example, the 24164 manufactured by ST). The protocol supports EEPROM addresses which can be selected using the 3 EEPROMadd[2:0] bits in the E9 register ...

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... POWER-ON SEQUENCE At power-on, the master interface runs a special sequence to build up the convergence cor- rection data and the STV2050A RAM is loaded with data from a user-specified EEPROM. 6.4 SECURITY FEATURE DURING DATA TRANFERS Since access to an EEPROM register is critical with respect to system performance, all EEPROM access commands in the E9 register, together with the corresponding addresses, are protected by the 2-bit, error-detecting Hamming code ...

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... STV2050A - MASTER I²C BUS INTERFACE – STX[0] =´EEPROM PROBLEM´ Read or Write sequence has been terminated with an access error, the STX[0] bit is set to low set back to high when the master starts the next R/W sequence. 6.6 DATA TRANSFER BETWEEN RAM AND EEPROM Data is transfered using the following I² ...

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... The I²C Master uses its own timebase with a local oscillator. The frequency is fixed by external filter (R1/C and R2) as shown in Typical values are: – – – Figure 14. Master I²C Clock STV2050A - MASTER I²C BUS INTERFACE Figure 14 "Master I²C Clock" on page STV2050A I2C MASTER Time Base 31. SCL ...

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... Used to easily adjust the gain of the convergence channels and to optimize interlace mode. – Auto-alignment Pattern: Supports an auto-alignment procedure. The video generator also produces the control signals for the optional optical loop functions. The patterns can be modified using several parameters in the registers of the STV2050A. 32/83 35. 37. ...

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... COV[2:0] bits in the EA register. If the control bit for one color is set to 0, the corresponding DAC output is switched to 0V. COV[2] COV[1] COV[0] The type of the pattern is selected by the PAS[4:0] bits in the EA register. PAS[4] PAS[3] PAS[2] STV2050A - VIDEO PATTERN GENERATOR SMALL CURSOR VISIB LE SCREEN zoom effect ...

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... STV2050A - VIDEO PATTERN GENERATOR PAS[1] PAS[0] The FBLK output is switched to ´high´ voltage when at least one color is activated by the COV bits in the EA register when the STA bit in the D7 register is activated color is selected, the FBLK output is switched to ´low´ voltage. For other features of the FBLK pin, refer to tion 8.4 " ...

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... Figure 17. Horizontal Grid Adjustment H-Flyback HSYNC Retrace Grid (HGP=0) HGP Grid (HGP>0) Retrace 7.2.2 Vertical Grid Adjustment In the same way, the vertical grid adjustment is done using the VGP[8:0] and VGD[5:0] bits in the D9 register. STV2050A - VIDEO PATTERN GENERATOR Figure 17 "Horizontal Grid Adjustment" on page Retrace 11 ...

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... STV2050A - VIDEO PATTERN GENERATOR Figure 18. Vertical Grid Adjustment If the VGP bit is programmed to 0, the grid starts with the first line following the two lines that are reserved for the register update procedure. The allowed range for the VGP is included between the 0 and 511 video lines. ...

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... The position of the horizontal border lines is identical to the horizontal grid lines at posi- 00h tions 0 and 12. The horizontal border lines move toward the centre of the screen by BPV video lines. 01h to 1Fh The allowed range for the BPV value is one vertical grid distance. STV2050A - VIDEO PATTERN GENERATOR Grid ...

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... STV2050A - VIDEO PATTERN GENERATOR Figure 20. Vertical Border Lines No te: The value of the BPV bit must be smaller than that of the VGD bit. 7.5 GAIN ADJUSTMENT LINES The “Gain Adjustment Lines” pattern is used mainly for 2 purposes: – To calibrate the convergence currents in order to achieve a consistent geometrical correction on the screens of a series of PTVs, – ...

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... TV field. Figure 22. Video Pattern for Vertical Gain Cursor Vertical Grid Line Number 8 Horizontal Grid Line Number 6 Additional Line Even Field STV2050A - VIDEO PATTERN GENERATOR Number 8 Vertical Grid Line Number 8 Horizontal Grid Line Number 6 Odd Field Section 9.7 49. ...

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... STV2050A - VIDEO PATTERN GENERATOR 7.6 AUTO-ALIGNMENT PATTERN The auto-alignment pattern is a rectangular, highlighted part of a screen with a constant brightness (horizontal brightness). See The On/Off is controlled by the PAS[4] bit in the EA register PAS[4] The size and the position of the pattern can be controlled by the EB and EC registers. The pat- tern is defined by its horizontal and vertical start and stop values: HO1, HG1, HO2, HG2, VO1, VG1, VO2 and VG2 ...

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... The pattern may be defined so that an end value is less than the start value. In this case, the window will wrap around through the retrace without any interruptions (two or four rectangles will be highlighted on the screen). The auto-alignment pattern signal is influenced by the horizontal or vertical blanking function. STV2050A - VIDEO PATTERN GENERATOR 41/83 ...

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... STV2050A - BLANKING OF VIDEO SIGNALS 8 BLANKING OF VIDEO SIGNALS The output of the RGB signals can be set to 0V during the horizontal and vertical retrace. The function is controlled by the D6 register. The horizontal and vertical retrace blanking function can be enabled independently. 8.1 HORIZONTAL BLANKING The HBE bit in the D6 register is used to enable/disable the horizontal blanking. ...

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... HVB and VVB bits as described in the following sections. HAE VAE 8.4 FAST BLANKING The FBLK pin is used to provide a fast switching signal that selects the source of the video signal to be displayed on the screen. Features are controlled by the D7 register. STA TVH STV2050A - BLANKING OF VIDEO SIGNALS V-Gridlines blank stop ...

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... STV2050A - BLANKING OF VIDEO SIGNALS TVV FAS The TVH and TVV bits are designed to be used, for example, in front projection applications. They are used to cut off TV video information at the left and right edges, as well as at the top and the bottom of the projection area that belongs to the overscan region in standard TV sets. ...

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... CONVERGENCE The STV2050A generates convergence values from parameters which are stored in the em- bedded RAM after having being loaded down from the EEPROM. These parameters can be: – Common for the entire screen area for each color. They are called “common values”. They are used for global adjustments, as they have the same effect on all the convergence values of the same color and in the same direction (horizontally or vertically) ...

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... STV2050A - CONVERGENCE 9.1.1 Position Offset (also called “static”) This value is added to each dynamic value of the corresponding channel used to reach an optimal dynamic value range, and to make a first rough correction. E1 Register: Horizontal SRH[7:0] SGH[7:0] SBH[7:0] E2 Register: Vertical SRV[7:0] SGV[7:0] SBV[7:0] The Position offset values are in two’s complement. ...

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... Blue Channel Red Channel Green Channel Blue Channel Section 9.6 "NORMAL TV OPERATION MODE" on page Section 4.1 "CONVERGENCE CORRECTION VALUES" Binary Code MSB --> LSB ’00 0000 0000’ ’10 0000 0000’ ’11 1111 1111’ interlace 1 = Interlace mode STV2050A - CONVERGENCE 55). 47/83 48. ...

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... Vertical Filter A vertical interpolation is performed by the STV2050A in order to provide a smooth correction transition between the stored points. A complex algorithm is implemented in order to improve the interline geometrical aspect, even when not aligned during chassis production or by the end user ...

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... The manual measuring line mode is enabled using the MLE bit in the D5 register. MLE This may be programmed when the measuring line is inserted using the MLN[8:0] bits in the D5 register. This signal is made available on pin 75 (MLIN). 0: Offset values 1: Normal operation 0: Manual measuring line disabled 1: Manual measuring line enabled STV2050A - CONVERGENCE 45. 26, only the field 55.) 49/83 ...

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... Figure 27 "Gain Cursors" on page This mode is normally used in conjunction with the corresponding video pattern. (Refer to tion 7.5 "GAIN ADJUSTMENT LINES" on page The STV2050A can generate a special convergence signal (cursor) controlled by the GCD bit in the E3 register. GCD The cursor action is selected by the DHV bit in the E3 register. ...

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... Vertical Gain Adjustment When using this mode, the STV2050A must be correctly set in order to recognize the inter- laced field. The IIE bit in the DA register must be set to 1. 9.8 CONVERGENCE OUTPUTS The values of the six convergence channels are converted by 14-bit DACs with a differential current output ...

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... STV2050A - CONVERGENCE Figure 28. Convergence Channel Structure Calibrated sources are used to generate the reference current for all CONVERGENCE and FOCUS DACs. The reference current is defined as page 61.) The outputs can be disabled using the CDO bit in the E3 register. CDO Notes: 1. The CDO bit is a common control for the convergence AND the focus outputs. ...

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... The hardware is not equipped with a safeguard device against DAC range overflow. This may occur if the FV2 bit is near the max. positive or negative value and the parabola is not symmetrical to the FV2 centre value. Also, large values for the FSB have to be taken into account. STV2050A - DYNAMIC FOCUS Figure 29 "Focus Parabola" FV3 ...

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... STV2050A - DYNAMIC FOCUS 10.2 FOCUS OUTPUTS The focus output signal is delivered on the FOCS pin. This output is normally used together with a static reference generated on the FOCR pin. This static reference corresponds to the mid-range code value. Figure 30. Focus Outputs STV2050A Focus W aveform Generator ...

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... However, aging and temper- ature can cause drifting, and the correction values may have to be adjusted. In order to avoid a manual after-sales re-alignment, the STV2050A can perform an automatic update of the field offset canceller values, as well as for the gain correction values. ...

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... STV2050A - ELECTRICAL LOOP A measuring line is inserted in each frame for measuring either the offset or the gain of the am- plifiers. Therefore, the compensation procedure has to run through the offset/gain measure- ment and horizontal/vertical channels sequentially. The right comparator is activated by the timing of the signals on the OGAV and OGAH pins. (Refer to Programming is possible when the measuring line is inserted using the MLN[8:0] bits in the D5 register ...

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... OPERATION OF THE ELECTRICAL LOOP The electrical loop is started by the STV2050A reset procedure following the readout of the EEPROM and the updating of the IC registers once the convergence outputs are enabled (the S02 and S03 bits in the E3 register are set to 1). If loop operation is enabled with the OLE and GLE bits, the loop sets the RU1 and RU2 bits to Low in the EF register which disables the RAM updating the D0* ...

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... STV2050A - ELECTRICAL LOOP 11.5.2 OGAH and OGAV Pins The OGAH (pin 57) and OGAV (pin 58) pins are multi-level output pins. In addition to the normal digital output function (logical “0” and “1”), they can drive a very stable current and can be switched to high impedance. The stable current and the high impedance can be used to generate the reference voltage across a grounded resistor for the gain and offset detection comparators ...

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... The OPPT pin is a port normally used as an output, and can deliver a logical electrical signal with a programmable time limit. – The OPTI pin is an input port for logical levels. This port is sampled by the STV2050A to indicate the status of the sensor. 12.2 OPTT SENSOR PORT CONTROL The OPTT sensor port can be programmed as an input output by the ODS in the E5 register ...

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... STV2050A - OPTICAL LOOP 12.2.1 OPTT Pin used as an Input The status of OPTT is available in S05 in register E5. S05 12.2.2 OPTT Pin used as an Output The OPTT output can either be forced to the electrical “1” level, or can be programmed in the same way as the auto-alignment pattern. This is carried out by the OOS bit in the E5 register. ...

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... CURRENT REFERENCE The STV2050A delivers accurate and stabilized currents used to drive the convergence and focus functions. It has an embedded voltage reference (band gap), which is used to generate a reference current (I ) refN The nominal voltage on the REFN pin is 500 mV. The Irefn current must be adjusted to 500 uA ...

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... The STV2050A can prevent overcurrents in the convergence coils, or poor programming, using the following controls: – At power-on reset, or after a reset, all analog outputs are disabled, and the STV2050A waits until at least 2 pulses of each horizontal and vertical signals are received. – As long as the internal set-up is not achieved, the outputs remain disabled. The setup dura- tion is typically 2 field periods. – ...

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... PPL During normal operation it is pulled down to ground: – if the STV2050A detects a malfunction such as a parity check error or power on reset error. – until the power-on reset is released. Otherwise, POUT is set to high impedance. In this case, the logical status of the POUT pin can be read using the S02 bit in the E3 register ...

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... Wait for fields after all the data has been downloaded and enable the outputs STATUS REGISTERS Some registers of the STV2050A can be read via the I²C slave bus in order to indicate the up- dated status of the IC. The update is enabled using the RUE bit in the EF register. ...

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... Adjustable voltage range Temperature drift (10°C to 70°C) Min. 10 -25 Min. 3.0 Figure 4 "Application Circuit" on page Min. Typ. Max. 100 Min. Typ. Max. 0.45 0.55 45 STV2050A - BUS EXPANDER Typ. Max. Unit 3 °C 125 °C Typ. Max. Unit 3.3 3.6 V 450 mW 8. ...

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... STV2050A - ELECTRICAL CHARACTERISTICS 20.3 VIDEO PATTERN OUTPUTS 20.3.1 DACs for RGB Parameter Resolution Output voltage DNL INL Matching between DACs Rise time (10...90%) Fall time (10...90%) Delay between video DACs (50%) 20.3.2 FBLK Output Parameter Output voltage low Output voltage high Rise/Fall time (10...90%) 20 ...

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... Internal parasitic capacitance on each DAC output Signal / Noise ratio Temperature drift of full scale output current 20.6 PLL Parameter Number of System Clock pulses per line 20.7 MASTER I²C TIME BASE Parameter SCL Frequency STV2050A - ELECTRICAL CHARACTERISTICS Min Typ Max +15 refN 2 0.5 -5 ± 0.2 ± ...

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... STV2050A - ELECTRICAL CHARACTERISTICS 20.8 HORIZONTAL AND VERTICAL SYNCHRONIZATION INPUTS Parameter Threshold V UP Threshold difference V - DOWN V UP Temperature drift 20.9 TBU OUTPUTS Parameter Output voltage at low level (logical “0”) Output voltage at high level (logical “1”) 20.10 ELECTRICAL LOOP PADS Parameter Output voltage at low level (logical “ ...

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... A A1 0.25 A2 2.55 B 0.30 C 0.13 D 22.95 D1 19. 16.95 E1 13. 0° STV2050A - PACKAGE MECHANICAL DATA seating plane mm Typ Max Min 3.40 0.010 2.80 3.05 0.100 0.45 0.012 0.23 0.005 23.20 23.45 0.904 20.00 20.10 0.783 18.40 17.20 17.45 0.667 14.00 14.10 ...

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... STV2050A - ELECTRICAL PIN CONFIGURATION 22 ELECTRICAL PIN CONFIGURATION Pin Name 19 VCCD 26 VCCF 42 VCCH 44 VCCG 50 VCCA 62 VCCB 70 VCCC Pin Name VDD 8 SDAI 9 SCLS 11 TEST 13 REST GND 27 SYNH 28 SYNV 71 ADS0 72 OPTI 70/83 Pin Name 41 GNDH 47 GNDA 67 GNDC GND Pin Name VDD 7 SDAO GND VDD ...

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... SCLM 10 VBLK 33 TBU0 34 TBU1 GND 35 TBU2 36 TBU3 37 TBU4 38 TBU5 39 TBU6 40 TBU7 74 OPTT 75 MLIN 78 PORC 79 PORB 80 PORA STV2050A - ELECTRICAL PIN CONFIGURATION Pin Name 57 OGAH Pad 58 OGAV Pin Name 3 GNDQ VDD 15 GNDN 30 GNDL GND VDD GND Pin Name 5 VCCQ 6 VCCK 12 VCCN VDD Pad ...

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... STV2050A - ELECTRICAL PIN CONFIGURATION Pin Name 31 VCCJ 32 VCCL 73 VCCM 72/83 Pin Name 4 GNDK 20 GNDD VDDE 29 GNDJ 59 GNDB 76 GNDM GND VDD GND ...

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... STV2050A - I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION 23 I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION A ACL Auto Calibration system cLock............................................................................D8 ACW Auto Calibration Window.....................................................................................D8 ADS Adjustment Data Set ...........................................................................................E9 AFS Number of calibrated cells per line......................................................................D8 AIE AutoIncrement Enable.........................................................................................E7 AMS Autocalibration Mode Selection...........................................................................D5 ASP Autocalibration Start Position ...

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... STV2050A - I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION EEPROM addEEPROM address ..................................................................................E9 F FAS FASt blanking enable ..........................................................................................D7 FIN Fast compensation of electrical loop.................................................................. DF FSB Focus Stop Bottom............................................................................................. DA FSO Filter Switched Off during horizontal retrace .......................................................D8 FV1 Focus parabola top value................................................................................... DE FV2 Focus parabola middle value ............................................................................. DE FV3 Focus parabola bottom value ...

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... STV2050A - I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION HRD Horizontal Retrace Distance ...............................................................................D8 HVB Horinzontal Video Blanking position....................................................................D6 HVM Horintal or Vertical Measurement.................................................................. D4,E4 I ICV Interlace Correction Value.................................................................................. DA IFA Interlace Field choice ......................................................................................... DA IIE Interlace enable.................................................................................................. DA M MLE Manual Measuring Line Enable...........................................................................D5 MLN Measuring Line Number......................................................................................D5 MSY ...

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... STV2050A - I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION PIC Status of the port PORC .....................................................................................E4 PLT Port latch timing ............................................................................................ D4,E4 PMH Parity of register DC values ................................................................................D5 PMV Parity of register DD values ................................................................................D5 POA Port A output data ......................................................................................... D4,E4 POB Port B output data ......................................................................................... D4,E4 POC Port C output data ......................................................................................... D4,E4 PPL Security output enable ...

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... STV2050A - I²C BUS REGISTER VARIABLE GLOSSARY AND REGISTER LOCATION T TBU BUS expander.....................................................................................................FE TE1 ............................................................................................................................E7 TE2 ............................................................................................................................EF TE3 ............................................................................................................................EF 77/83 ...

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... STV2050A - INDEX OF I²C BUS REGISTERS 24 INDEX OF I²C BUS REGISTERS A ACL .............................................................................................................................................19, 23, 24 ACW ..................................................................................................................................................19, 24 ADS .................................................................................................................................13, 27, 28, 61, 62 AFS ...................................................................................................................................................19, 24 AIE .....................................................................................................................................................14, 20 AMS ..................................................................................................................................................19, 24 ASP ...................................................................................................................................................19 BCH ..................................................................................................................................................19, 45 BCV ...................................................................................................................................................19, 45 BFH ...................................................................................................................................................19, 45 BFV ...................................................................................................................................................19, 45 BGA ............................................................................................................................................19, 60, 64 BPH ...................................................................................................................................................19, 36 BPV .............................................................................................................................................19, 36 CBH ............................................................................................................................................19, 48, 49 CBS ...

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... HAM ............................................................................................................................................20, 61, 62 HBE ...................................................................................................................................................19, 41 HDP ..................................................................................................................................................19, 23 HG1 ...................................................................................................................................................20, 39 HG2 ...................................................................................................................................................20, 39 HG3 ...................................................................................................................................................20, 59 HG4 ...................................................................................................................................................20, 59 HGD ................................................................................................................................19, 22, 23, 34, 41 HGP ..................................................................................................................................................19, 34 HIF .....................................................................................................................................................19, 47 HO1 ...................................................................................................................................................20, 39 HO2 ...................................................................................................................................................20, 39 HO3 ...................................................................................................................................................20, 59 HO4 ...................................................................................................................................................20, 59 HRD ............................................................................................................................................19, 22, 34 HVB .............................................................................................................................................19, 41, 42 STV2050A - INDEX OF I²C BUS REGISTERS 79/83 ...

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... OBV ..................................................................................................................................................19, 46 ODS ..................................................................................................................................................20, 58 ODT ..................................................................................................................................................20, 59 OGH ..................................................................................................................................................19, 46 OGV ..................................................................................................................................................19, 46 OLE .............................................................................................................................................19, 55, 56 OOS ..................................................................................................................................................20, 59 OPI ....................................................................................................................................................20, 59 OPTT_PATTERN .................................................................................................................................59 ORG ........................................................................................................................................................46 ORH ........................................................................................................................................................19 ORV ..................................................................................................................................................19 PAS .......................................................................................................................................20, 32, 35, 39 PBH ...................................................................................................................................................19, 33 PBV ...................................................................................................................................................19, 33 PDA .............................................................................................................................................19, 20, 56 PDB .............................................................................................................................................19, 20, 56 PDC ............................................................................................................................................19, 20, 56 PIA ...........................................................................................................................................................20 STV2050A - INDEX OF I²C BUS REGISTERS 80/83 ...

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... S03 ....................................................................................................................................................20, 56 S05 ....................................................................................................................................................20, 59 S09 ..........................................................................................................................................................20 S10 ....................................................................................................................................................20, 25 S11 ....................................................................................................................................................20, 59 S12 ..........................................................................................................................................................20 S13 ....................................................................................................................................................20, 25 S14 ....................................................................................................................................................20, 25 S19 ..........................................................................................................................................................20 SBH ...................................................................................................................................................19, 45 SBV ...................................................................................................................................................19, 45 SGH ..................................................................................................................................................19, 45 SGV ..................................................................................................................................................19, 45 SRH ..................................................................................................................................................19, 45 SRV ...................................................................................................................................................19, 45 SSE .........................................................................................................................................................20 STA .......................................................................................................................................19, 28, 29, 33 STL ..............................................................................................................................................20, 54, 56 STV2050A - INDEX OF I²C BUS REGISTERS 81/83 ...

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... VAE ...................................................................................................................................................19, 42 VBE .........................................................................................................................................................19 VDC ..................................................................................................................................................20, 33 VFP ...................................................................................................................................................19, 52 VG1 ...................................................................................................................................................20, 39 VG2 ...................................................................................................................................................20, 39 VG3 ...................................................................................................................................................20, 59 VG4 ...................................................................................................................................................20, 59 VGD ......................................................................................................................................19, 34, 42, 52 VGP ............................................................................................................................................19, 34, 35 VHV ...................................................................................................................................................20, 37 VO1 ...................................................................................................................................................20, 39 VO2 ...................................................................................................................................................20, 39 VO3 ...................................................................................................................................................20, 59 VO4 ...................................................................................................................................................20, 59 VST ...................................................................................................................................................19, 25 VVB .............................................................................................................................................19, 41, 42 STV2050A - INDEX OF I²C BUS REGISTERS 82/83 ...

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... I C system is granted provided that the system conforms to the I Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain STV2050A - INDEX OF I²C BUS REGISTERS 2003 STMicroelectronics - All Rights Reserved Standard Specification as defined by Philips. STMicroelectronics Group of Companies Sweden - Switzerland - United Kingdom - U ...