MAX9257 Maxim, MAX9257 Datasheet
MAX9257
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MAX9257 Summary of contents
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... The clock is recovered from input serial data at MAX9258, hence eliminating the need for an external reference clock. The MAX9257 serializes 10, 12, 14, 16, and 18 bits with the addition of two encoding bits for AC-coupling. The MAX9258 deserializer links with the MAX9257 to deseri- ...
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... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAX9257 DC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V 50Ω ...
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... Fully Programmable Serializer/Deserializer MAX9257 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL Low-Level Output Voltage Output Short-Circuit Current 2 I C/UART I/O Input Leakage Current High-Level Input Voltage SDA/RX Low-Level Input Voltage SDA/RX Low-Level Output Voltage SCL, SDA ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel MAX9257 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL POWER SUPPLY Worst-Case Supply Current (Figure 8pF, 12 bits L Sleep Mode Supply Current 4 _______________________________________________________________________________________ = -40°C to +105°C, unless otherwise noted. Typical values are at V ...
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... Fully Programmable Serializer/Deserializer MAX9257 AC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL PCLK_IN TIMING REQUIREMENTS Clock Period Clock Frequency Clock Duty Cycle Clock Transition Time SWITCHING CHARACTERISTICS LVDS Output Rise Time LVDS Output Fall Time t R1A ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel MAX9257 AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL Low Period of SCL Clock High Period of SCL Clock Repeated START Condition t SU:STA Setup Time Data Hold Time t HD:DAT Data Setup Time ...
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Fully Programmable Serializer/Deserializer MAX9258 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, differential input voltage |V CC_ /2 -40°C to +105°C, unless otherwise noted. Typical values are at V ...
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... PUD t (Figure 13) PDD Each half of the UI, 12 bit, t SRATE = 840Mbps, PRBS No spread JT pattern (Figure 15 Max data rate = 400kbps. Typical Operating Characteristics = +25°C, unless otherwise noted.) MAX9257 SUPPLY CURRENT vs. FREQUENCY 140 PRBS PATTERN 10-BIT 120 100% PREEMPHASIS 100 PREEMPHASIS ...
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... PCLK FREQUENCY (MHz vs. BIT ERROR RATE (< 10 900 800 2% SPREAD ON MAX9257, STP CABLE 700 100% PREEMPHASIS NO PREEMPHASIS 600 500 -12 FOR BER CAN BE AS LOW AS 10 CABLE LENGTHS LESS THAN 10m. 400 ...
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... Serial LVDS Inverting Output Serial LVDS Noninverting Output LVDS Supply Voltage. Bypass V CCLVDS parallel as close as possible to the device with the smallest value capacitor closest CCLVDS MAX9257 Pin Description FUNCTION to GND with 0.1µF and CCIO to GND with 0.1µF and 0.001µF capacitors FPLL assed ...
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... PRBS errors. Pull LVCMOS/LVTTL Control Channel UART Output ______________________________________________________________________________________ 2 with UART/I MAX9257 Pin Description (continued) Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to follow V . Connect REM high to V through 10kΩ resistor for remote power-up. REM internally pulled down to GND ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel PIN NAME 16 TX LVCMOS/LVTTL Control Channel UART Input internally pulled Open-Drain Lock Output. LOCK asserts high to indicate PLLs are locked with correct serial-word 17 ...
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... Fully Programmable Serializer/Deserializer SDO- V (-) OS SDO+ V (-) OD (SDO+) - (SDO-) Figure 1. MAX9257 LVDS DC Output Parameters V OUT V V HYST+ HYST Figure 2. Input Hysteresis ______________________________________________________________________________________ 2 with UART/I C Control Channel SDO SDO ((SDO+) + (SDO-))/2 V (+) (+) - V (-) ∆ (+) ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel (SDO+) - (SDO-) Figure 4. MAX9257 LVDS Control Channel Output Load and Output Rise/Fall Times PCLK_IN DIN, VSYNC_IN, HSYNC_IN Figure 5. MAX9257 Input Setup and Hold Times 14 ______________________________________________________________________________________ SDO+ SDO 80% 20% t RISE V ILMAX t SET V IHMIN ...
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... Fully Programmable Serializer/Deserializer DIN, HSYNC_IN, N N+1 VSYNC_IN PCLK_IN SDO Figure 6. MAX9257 Parallel-to-Serial Delay PCLK_IN t F Figure 7. MAX9257 Parallel Input Clock Requirements PCLK_OUT DOUT NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE. Figure 8. MAX9258 Worst-Case Pattern Output ______________________________________________________________________________________ 2 with UART/I C Control Channel EXPANDED TIME SCALE N+2 ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel PCLK_OUT Figure 10. MAX9258 Clock Output High and Low Time PCLK_OUT DOUT, VSYNC_OUT, HSYNC_OUT, LOCK Figure 11. MAX9258 Output Data Valid Times V PD IHMIN t PUD POWERED DOWN Figure 12. ...
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Fully Programmable Serializer/Deserializer SERIAL-WORD LENGTH SERIAL WORD N SDI FIRST BIT DOUT, HSYNC_OUT, PARALLEL WORD N-2 VSYNC_OUT PCLK_OUT NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 14. MAX9258 Serial-to-Parallel Delay +25mV -25mV NOTE ONE SERIAL BIT. TIME INPUT ...
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... MAX9257 accepts parallel video data and transmits serial encoded data over the LVDS link. The MAX9258 accepts the encoded serial LVDS data and converts it back to parallel output data. The MAX9257 has dedicated inputs for HSYNC and VSYNC. The selected VSYNC edge causes the MAX9257/MAX9258 to enter the control channel phase ...
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... VSYNC_IN SDI/O± VIDEO SPREAD PROFILE SDI/O± CCEN Figure 20. Video and Control Channel Phases (MAX9257 Spread is Enabled) ______________________________________________________________________________________ 2 with UART/I C Control Channel the control channel is open. Programmable timers and ECU signal activity determine how long the control channel stays open. The timers are reset by ECU signal activity ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel Table 1. MAX9257 Power-Up Default Register Map (see the MAX9257 Register Table ) REGISTER REGISTER NAME ADDRESS (hex) REG0 0x00 REG1 0x01 REG2 0x02 REG3 0x03 REG4 0x04 REG5 0x05 REG6 0x06 REG7 0x07 REG8 0x08 ...
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... Fully Programmable Serializer/Deserializer Table 1. MAX9257 Power-Up Default Register Map (continued) REGISTER REGISTER NAME ADDRESS (hex) REG11 0x0B REG12 0x0C REG13 0x0D REG14 0x0E Table 2. MAX9258 Power-Up Default Register Map (see the MAX9258 Register Table ) REGISTER REGISTER NAME ADDRESS (hex) REG0 0x00 ...
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... SDO+, SDO- SCL/TX, SDA/RX, REM Table 4. MAX9258 I/O Supply INPUTS/OUTPUTS All inputs and outputs SDI+, SDI- word width, serial frequency range, parity, spread-spec- trum, and pixel clock frequency range ( see the MAX9257 Register Table and the MAX9258 Register Table) . SUPPLY V CCIO V CCLVDS ...
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Fully Programmable Serializer/Deserializer Table 5. Serial Video Data Format for 20-Bit Serial-Word Length (Parallel-Word Width = 18) BIT NAME EN0 EN1 HSYNC VSYNC D0 Table 6. Serial Video Data Format for 18-Bit Serial-Word Length (Parallel-Word Width ...
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... PCLK_IN (Table 14). If the pixel clock frequency needs to change to a frequency outside the pro- grammed range, the ECU must program both the MAX9257 and the MAX9258 in the same control chan- nel session. Serial-Data Rate Range The word length and pixel clock is limited by the maxi- mum serial-data rate of 840Mbps ...
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... MAX9258 VSYNC active edge must also be pro- grammed for rising edge to reproduce VSYNC rising edge at the MAX9258 output. However, matching the polarity of the VSYNC active edge between the MAX9257 and the MAX9258 is not a requirement for proper operation. HSYNC: HSYNC active-edge polarity is programmable for the MAX9258. ...
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... LOCK is high impedance when the MAX9258 is locked to the MAX9257 and remains high under the locked condition. When the devices are in shutdown, the channel is not locked and LOCK goes high impedance, is pulled high, and should be ignored ...
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... UART pack- ets in the reverse direction. ECU can disable communi- cation to the peripheral device by writing INTEN (REG8[6] in the MAX9257 and REG7[6] in the MAX9258). Base mode is the default mode. Bypass mode is entered by writing INTMODE and 1 to INTEN (Table 23). ...
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... The ETO (end timeout) timer closes the control channel if the ECU stops communicating for the ETO timeout period. Configure register REG3[7:4] for both the MAX9257 and the MAX9258 to select the divide ratio (ETODIV) for the ETO clock as a function of the pixel clock (Table 25). The timeout period is determined by ...
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... ETOCNT is 0. That means the ETO timeout period is equal to 1,024 pixel clock cycles. Closing the Control Channel After the MAX9257 detects the active VSYNC edge, it sends three synchronization words. Once the MAX9258 sees the active VSYNC transition and detects three syn- chronization words, it enters the control channel phase and CCEN goes high ...
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... If MAX9257 receives the lock frame, it understands that the MAX9258 locked state and sends a short training sequence. If the lock frame is not received by the MAX9257, it assumes that the MAX9258 is not locked and sends a long train- ing sequence. After the short or long training sequence is complete, the MAX9257 sends three special synchro- nization words before entering the video phase ...
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... When the control channel is open, the ECU writes to the PD bit to power down the MAX9257. In this case, to power up the MAX9257 again, the power-up sequence explained in the Remote Power-Up of the MAX9257 (REM = Pulled MAX9258 has a PD input that powers down the device ...
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... If the MAX9257 does not receive the lock frame, it transmits a long synchronization pattern before the start of next video phase. When REM = 1, if the lock frame is not received by the MAX9257 after 62 consec- utive attempts to synchronize, SEREN is disabled so that the control channel opens permanently for trou- bleshooting ...
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... The MAX9257 receives I device and converts them to UART packets to send back to the ECU. To disable communication to the peripheral device, write INTEN (REG8[6] in the MAX9257 and REG7[6] in the MAX9258). In base mode, the STO/ETO timers and the EF command are used to control the duration of the control channel. ...
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... BYPASS MODE CHANNEL T1 = TIME TO ENTER CONTROL CHANNEL T2 = STO TIMER T3 = CTO TIMER T4 = ETO TIMER T5 = CONTROL CHANNEL EXIT TIME HSK = HANDSHAKING BETWEEN THE MAX9257 & THE MAX9258 = TIMER RESET Figure 24. CTO Timing UART-to-I 2 The UART-to-I C converter accepts UART read or write packets issued by the ECU and converts them master protocol when in base mode ...
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... UART Frame Format The UART frame used to program the MAX9257 and the MAX9258 has a low start bit, eight data bits, an even parity bit and a high stop bit. The data following the start bit is the LSB. With even parity, when there are an odd number the data bits (D0 through D7) the parity bit is set to 1 ...
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... REG8[5] in MAX9257 and REG7[5] in MAX9258 must be set high. Set the control channel data rate in base mode by writ- ing to REG8[1:0] in the MAX9257 and REG7[1:0] in the MAX9258. These write commands take effect in the next control channel. Programming the FAST bit takes effect in the same con- trol channel ...
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... The I scale with converter 2 C SCL clock The MAX9257/MAX9258 have built-in circuits for testing bit errors on the serial link. The MAX9257 has a PRBS generator and the MAX9258 has a PRBS checker. The 2 C read length of the PRBS pattern is programmable from word length or continuous by programming REG9[7:4] in the MAX9257 ...
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... Parity protection of video data is programmable for par- allel-word widths of 16 bits or less. When programmed, two parity bits are appended to each parallel word latched into the MAX9257. In the MAX9258, a 16-bit parity error counter logs parity errors. The ERROR out- put on the MAX9258 goes low if parity errors exceed a programmable threshold ...
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... Use high-frequency, surface-mount ceramic capacitors. Power-Supply Circuits and Bypassing + All single-ended inputs and outputs on the MAX9257 are powered from V the MAX9258 are powered from V V CCOUT ply. The input levels or output levels scale with these supply rails. ...
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... Control channel start timeout counter STOCNT Divided pixel clock is used to count up to (STOCNT + < 300ns. If the transition time BUS MAX9257 Register Table DESCRIPTION 0 = disabled (default enabled 100 = 18 101 = 18 (default) 110 = 18 111 = 18 100 = Off 101 = 3% 110 = 3 ...
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... Bypass filter PLL BYPFPLL 0 = active (default bypass Reserved (set to 0) PRBS test enable PRBSEN 0 = disabled (default enabled DEVICEID 7-bit address of MAX9257 Reserved (set End frame to close control channel Reserved (set to 1) DESID 7-bit address ID of MAX9258 Reserved (set Control Channel ...
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... MAX9257 Register Table (continued) NAME Interface mode INTMODE 0 = UART (default Interface enable INTEN 0 = disabled (default enabled Fast UART transceiver FAST ate = 4.25M efaul ate = 4.25M 10M ...
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... UART/I C Control Channel MAX9257 Register Table (continued) NAME LVDS driver preemphasis setting 000 = 20% 111 = off (default) 001 = 40% 101 = 20% PREEMP 010 = 60% 110 = 20% 011 = 80% 100 = 100% Reserved (set to 00000) Reserved (set to 000000 glitch filter setting ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel ADDRESS BITS DEFAULT 7 2:0 101 7 4:0 00000 Control channel start timeout: (STO) times out if ECU does not start ...
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Fully Programmable Serializer/Deserializer ADDRESS BITS DEFAULT Control channel end timeout: (ETO) times out if ECU does not use control channel for this amount of time after it has already used at least once. 3 7:4 1010 3:0 0000 7 0 ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel ADDRESS BITS DEFAULT 8 7:0 00010000 9 7:0 00000000 10 7:0 (RO) 11 7:0 (RO) 12 7:0 (RO) 7:5 (RO) 4 (RO) 3 (RO (RO) 1 (RO) 0 (RO) ...
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... ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic sys- tems. LVDS outputs on the MAX9257 and LVDS inputs on the MAX9258 meet ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All other pins meet the ...
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... SDA(RX) ±2% OR ±4% PCLK_OUT SPREAD PLL CLK OUT DECODE/ DOUT[0:15] DC BALANCE + FIFO HSYNC_OUT VSYNC_OUT BLANK DETECT/TIMER VSYNC POLARITY ______________________________________________________________________________________ MAX9257 SERIALIZER ±1.5% TO ±4% SPREAD PLL LVDS Tx 1x CLK OUT PARALLEL TO SERIAL + FIFO DIN WIDTH OSC CONTROL UART 2 Tx/ UART-TO-I ...
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... CCFPLL 22 GPIO9 N.C. 12 GPIO8 MAX9258 LQFP Pin Configurations N.C. 36 DIN0 35 34 REM V 33 CCLVDS SDO+ 32 SDO- 31 MAX9257 GND 30 LVDS GND 29 SPLL V 28 CCSPLL GPIO9 27 GPIO8 26 N.C. 25 LQFP N. DOUT7 DOUT8 34 DOUT9 33 DOUT10 32 DOUT11 31 DOUT12 30 DOUT13 29 DOUT14 28 GND ...
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... PCLK SERIAL HSYNC ECU I/O VSYNC LOCK MAX9258 TX μC RX CONTROL UNIT 50 ______________________________________________________________________________________ UP TO 20m CABLE LENGTH 100Ω 100Ω SERIALIZED DIGITAL VIDEO CONTROL CHANNEL Typical Operating Circuit 10 DATA PCLK SERIAL I/O HSYNC CMOS IMAGE VSYNC SENSOR MAX9257 SCL SDA REMOTE CAMERA ASSEMBLY ...
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... Fully Programmable Serializer/Deserializer Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 40 TQFN T4055+1 48 LQFP C48+3 ______________________________________________________________________________________ 2 with UART/I C Control Channel DOCUMENT NO. 21-0140 21-0054 51 ...
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... Added automotive qualified part numbers to Ordering Information. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...