AD9889KSTZ-80 Analog Devices Inc, AD9889KSTZ-80 Datasheet - Page 20

• Manufacturer Part Number: AD9889KSTZ-80
• Description: TRANSMITTER HDMI/DVI 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: HDMI, DVI Transmitterr

Specifications of AD9889KSTZ-80

• Applications: Recorders, Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9889
HDCP HANDLING
The AD9889 has a built-in microcontroller to handle HDCP
transmitter states, including handling downstream HDCP
repeaters. To activate HDCP from a system level, the main
controller needs to set R0xAF[7] to 1 to inform AD9889 that
the video stream should be encrypted. The AD9889 takes
control from there and implements all remaining tasks defined
by the HDCP 1.1 specification.
The system controller should monitor the status of HDCP by
reading Register R0xB8[6] (indicating the HDCP link has been
established). There are also some error flags (R0xC5[7] and
R0xC8[7:4]) to help debug the system.
The AD9889 also supports AV functions to suspend HDCP
temporarily. To set AV mute, clear R0x45[7] and set R0x45[6]
to 1. To clear AV mute, clear R0x45[6] and set R0x45[7] to 1.
(Note that it is invalid to set the two mute bits at the same time.)
For more information, refer to application note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
EDID READING
The AD9889 has an I
read the EDID based on system need. It buffers segment 0 once
HPD is detected. The system can request other segments by
programming Register R0xC4. An interrupt bit (R0x96[2])
indicates the completion of EDID rebuffering.
To read EDID data from the AD9889, use the AD9889
programming bus (Pin 46 and Pin 47) with I
This is the default address but can be changed by writing the
desired address into Register R0x43.
For more information, refer to application note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
2
C master (DDC Pin 44 and Pin 45) to
2
C Address 0x7E.
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INTERRUPTS
The AD9889 has interrupts to help with the system design: hot
plug detection, receiver sense, VS detection, audio FIFO
overflow, ITU 656 error, EDID ready, HDCP error, and BKSV
ready. Interrupts can be cleared by writing 1 into the interrupt
register (R0x96, R0x97). There are read-only registers (R0xC5,
R0xC6) to show the state of these signals. Masks (R0x94,
R0x95) are available to let the user selectively activate each
interrupt. To enable a specific interrupt register, write 1 to the
corresponding mask bit.
POWER MANAGEMENT
The AD9889 power-down pin polarity depends on the
AD9889’s I
active. To use 0x7A, the PD pin is low active. At any time, the
power-down pin polarity can be verified by reading Register
R0x42[7].
The AD9889 can be powered down or reset either by Pin 33 or
by Register R0x41[6]. During power-down mode, all the
circuits are inactive except the I
related to mode and activity detection. During power-down
mode, the chip status can still be read through the I
enter normal power-down mode, either drive Pin 33 to 1, or set
R0x41[6] to 1. To further reduce power consumption, disable
the receiver sense detection by setting Register R0xA4[2] to 1.
For HDCP security reasons, the I
reset by the power-down pin. Anytime after power down, the
user needs to drive the PD pin back to 0 and set R0x41[6] to
0 to activate the chip.
2
C address selection. To use 0x72, the PD pin is high
2
C slave and some circuits
2
C power-down bit is also
2
C slave. To