MAX9209 Maxim, MAX9209 Datasheet - Page 9

• Manufacturer Part Number: MAX9209
• Description: The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs
• Manufacturer: Maxim

Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
The MAX9209 operates at a parallel clock frequency of
8MHz to 34MHz in DC-balanced mode and 10MHz to
40MHz in non-DC-balanced mode. The MAX9213 oper-
ates at a parallel clock frequency of 16MHz to 66MHz
in DC-balanced mode and 20MHz to 85MHz in non-
DC-balanced mode.
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB/NC pin (see Table 1). In non-DC-
balanced mode, each channel serializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are serialized every clock cycle (7 data bits + 2 DC-bal-
ance bits). The highest data rate in DC-balanced mode
for the MAX9213 is 66MHz x 9 = 594Mbps. In non-DC-
balanced mode, the maximum data rate is 85MHz x 7 =
595Mbps. A bit time is 1 divided by the data rate, for
example, 1 / 595Mbps = 1.68ns.
Through data coding, the DC-balance circuits limit the
imbalance of ones and zeros transmitted on each chan-
nel. If +1 is assigned to each binary one transmitted
(SINGLE ENDED)
(SINGLE ENDED)
(SINGLE ENDED)
(DIFFERENTIAL)
_______________________________________________________________________________________
TxCLK OUT
TxOUT2
TxOUT1
TxOUT0
Detailed Description
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TxIN15
TxIN8
TxIN1
CYCLE N - 1
TxIN14
TxIN7
TxIN0
DC Balance
TxIN20
TxIN13
TxIN6
Programmable DC-Balanced
TxIN19
TxIN12
TxIN5
and -1 is assigned to each binary zero transmitted, the
variation in the running sum of assigned values is
called the digital sum variation (DSV). The maximum
DSV for the MAX9209/MAX9213 data channels is 10. At
most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
channel is 5. Limiting the DSV and choosing the correct
coupling capacitors maintain differential signal amplitude
and reduce jitter due to droop on AC-coupled links.
Table 1. DC-Balance Programming
MAX9209
MAX9213
TxIN18
TxIN11
TxIN4
DEVICE
CYCLE N
TxIN17
TxIN10
TxIN3
High or open
High or open
21-Bit Serializers
DCB/NC
TxIN16
Low
Low
TxIN9
TxIN2
TxIN15
TxIN8
TxIN1
OPERATING
DC balanced
DC balanced
balanced
balanced
Non-DC
Non-DC
MODE
TxIN14
TxIN7
TxIN0
FREQUENCY
OPERATING
10 to 40
16 to 66
20 to 85
8 to 34
(MHz)
9