MAX9209 Maxim, MAX9209 Datasheet - Page 11

• Manufacturer Part Number: MAX9209
• Description: The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs
• Manufacturer: Maxim

Figure 9. PLL Set Time
Figure 10. Power-Down Delay
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
To obtain DC balance on the data channels, the paral-
lel input data is inverted or not inverted, depending on
the sign of the digital sum at the word boundary. Two
complementary bits are appended to each group of 7
parallel input data bits to indicate to the MAX9210/
MAX9214 deserializers whether the data bits are invert-
ed (Figure 11). The deserializer restores the original
CYCLE N - 1
TxCLK OUT+
TxCLK OUT-
TxOUT2
TxOUT1
TxOUT0
DCA2
DCA1
DCA0
TxOUT_, TxCLK OUT
DCB2
DCB1
DCB0
PWRDWN
TxCLK IN
TxIN20
TxIN13
TxIN6
V
CC
______________________________________________________________________________________
TxIN19
TxIN12
TxIN5
HIGH-Z
TxOUT_, TxCLK OUT
TxIN18
TxIN11
TxIN4
PWRDWN
TxCLK IN
TxIN17
TxIN10
TxIN3
CYCLE N
TxIN16
TxIN9
TxIN2
2.0V
3.0V
TxIN15
TxIN8
TxIN1
Programmable DC-Balanced
TxIN14
TxIN7
TxIN0
V
TPPLS
OD
= 0
DCA2
DCA1
DCA0
state of the parallel data. The LVDS clock signal alter-
nates duty cycles of 4/9 and 5/9, which maintains DC
balance. Figure 12 shows the non-DC-balanced mode
inputs mapped to LVDS outputs.
DCB2
DCB1
DCB0
TxIN20
TxIN13
TxIN6
0.8V
TPDD
21-Bit Serializers
TxIN19
TxIN12
TxIN5
3.6V
TxIN18
TxIN11
HIGH-Z
TxIN4
CYCLE N + 1
TxIN17
TxIN10
TxIN3
TxIN16
TxIN9
TxIN2
DIFFERENTIAL 0
TxIN15
TxIN8
TxIN1
TxIN14
TxIN7
TxIN0
11