EL9115ILZ Intersil, EL9115ILZ Datasheet
EL9115ILZ
Specifications of EL9115ILZ
Available stocks
Related parts for EL9115ILZ
EL9115ILZ Summary of contents
Page 1
... Ld 5mmx5mm QFN (Note) (Pb-free) EL9115ILZ-T7* 9115ILZ 20 Ld 5mmx5mm QFN (Note) (Pb-free) EL9115ILZ-T13* 9115ILZ 20 Ld 5mmx5mm QFN (Note) (Pb-free) *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ...
Page 2
... Supply Current (Note 1) SP OFF I Output Drive Current OUT L Logic High HI L Logic Low LO 2 EL9115 Thermal Information = +25°C) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +5V -5V +25°C, exposed die plate = -5V, unless otherwise specified CONDITION X2 = 5V, 150Ω load Gain falls to 90% of nominal X2 = +5V 75Ω ...
Page 3
AC Electrical Specifications V PARAMETER DESCRIPTION BW -3dB 3dB Bandwidth BW 0.1dB 0.1dB Bandwidth SR Slew Rate Transient Response Time Voltage Overshoot OVER Glitch Switching Glitch THD Total Harmonic Distortion X Hostile Crosstalk t ...
Page 4
Pin Descriptions (Continued) PIN NUMBER PIN NAME 19 TESTR 20 X2 Thermal Pad Typical Performance Curves Delay = 62ns -3dB@80MHz Delay 10, 20, 30, 40 and 50ns FIGURE 1. GAIN vs FREQUENCY DELAY TIME (ns) FIGURE 3. TYPICAL DC OFFSET ...
Page 5
Typical Performance Curves Vout = 1Vptp FIGURE 7. DISTORTION vs FREQUENCY X2 Hi_62ns Delay X2 Hi_0ns Delay X2 Low_62ns Delay X2 Low_0ns Delay FIGURE SUPPLY JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.0 ...
Page 6
R_IN 2 G_IN 4 B_IN 6 9 SDATA 10 SCLOCK 8 NSENABLE Applications Information EL9115 is a triple analog delay line receiver that allows skew compensation between any three high frequency signals. This part compensates for time skew introduced by ...
Page 7
TABLE 1. SERIAL BUS DATA (Continued) vwxyz 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 NOTE: Delay register word = 0abvwxyz; Red register ...
Page 8
Signals A and B are derived from the video input by comparing the video signal with a slicing level, which is set by an internal DAC. This enables the delay to be measured either from the rising edges of sync-like ...
Page 9
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...