TDA18211HD/C2,551 NXP Semiconductors, TDA18211HD/C2,551 Datasheet - Page 12
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TDA18211HD/C2,551
Manufacturer Part Number
TDA18211HD/C2,551
Description
IC TV SILICON TUNER 64-HLQFN
Manufacturer
NXP Semiconductors
Type
Silicon Tunerr
Datasheet
1.TDA18211HDC2518.pdf
(66 pages)
Specifications of TDA18211HD/C2,551
Package / Case
*
Applications
Set-Top Boxes
Mounting Type
Surface Mount
Bus Type
I2C
Maximum Agc
80 dB
Maximum Frequency
864 MHz
Minimum Frequency
174 MHz
Modulation Technique
QAM
Mounting Style
SMD/SMT
Function
TV
Noise Figure
5.5 dB
Operating Supply Voltage
3.3 V
Supply Voltage (min)
3.13 V
Supply Voltage (max)
3.47 V
Minimum Operating Temperature
0 C
Maximum Operating Temperature
+ 70 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935285061551
TDA18211HD/C2-S
TDA18211HD/C2-S
TDA18211HD/C2-S
TDA18211HD/C2-S
NXP Semiconductors
Table 7.
TDA18211HD_5
Product data sheet
Address Byte
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Extended bytes
10h
13h
15h
17h
19h
1Bh
1Ch
1Dh
21h
23h
24h
25h
26h
CD1
CD2
CD3
MPD IF_NOTCH
MD1
MD2
MD3
EB1
EB4
EB6
EB8
EB10 CID_GAIN[5:0]
EB12 PD_AGC1_DET
EB13 RFC_K[2:0]
EB14 RFC_CPROG[7:0]
EB18 AGC1_LOOP_OFF
EB20 FORCE_LOCK
EB21 AGC2_LOOP_OFF
EB22 RF_TOP[2:0]
EB23 FORCELP_FC2_EN
I
2
C-bus registers bits explanation
Symbol
CAL_DIV[22:16]
CAL_DIV[15:8]
CAL_DIV[7:0]
MAIN_POST_DIV[6:0] LO synthesizer post-divider bits
MAIN_DIV[22:16]
MAIN_DIV[15:8]
MAIN_DIV[7:0]
CALVCO_FORLON
AGC1_ALWAYS_
MASTERN
AGC1_FIRSTN
LO_FORCESRCE
CAL_FORCESRCE
CID_ALARM
PD_AGC2_DET
RFC_M[1:0]
AGC1_GAIN[1:0]
AGC2_GAIN[1:0]
IF_TOP[3:0]
LP_FC[2]
Description
calibration synthesizer main divider bits
calibration synthesizer main divider bits
calibration synthesizer main divider bits
adds a DC notch in IF for a better adjacent channels rejection;
depends on standards
LO synthesizer main divider bits
LO synthesizer main divider bits
LO synthesizer main divider bits
determines which VCO is used during Normal mode operations
enables AGC1 normal operation whatever the tuner type (master or
slave)
determines which AGC (1 or 2) will be detected when detectors 1
and 2 are up
forces the main PLL charge pump to source current to the main PLL
loop filter
forces the calibration PLL charge pump to source current to the
calibration PLL loop filter
indicates that signal sensed by the power detector used during
calibrations is out of range
calibration power detector output
power-down of AGC1 detector
power-down of AGC2 detector
parameter used during the RF tracking filters calibration
parameter used during the RF tracking filters calibration
tuning word of the RF tracking filters
turns off the AGC1 loop
AGC1 gain
forces the internal lock indicator to logic 1
turns off the AGC2 loop
AGC2 gain
Take Over Point (TOP) of the RF AGC, detection in RF
TOP of the RF AGC, detection in IF
1.5 MHz bandwidth filter selection
…continued
Rev. 05 — 2 June 2009
TDA18211HD
DVB-T Silicon Tuner IC
© NXP B.V. 2009. All rights reserved.
Reference
Table 20
Table 20
Table 20
Table 21
Table 22
Table 22
Table 22
Table 23
Table 23
Table 23
Table 23
Table 23
Table 23
Table 23
Table 23
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Table 23
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