LMH0307GRE/NOPB National Semiconductor, LMH0307GRE/NOPB Datasheet - Page 12

IC CBL DVR DUAL HD/SD 25-UARRAY

LMH0307GRE/NOPB

Manufacturer Part Number
LMH0307GRE/NOPB
Description
IC CBL DVR DUAL HD/SD 25-UARRAY
Manufacturer
National Semiconductor
Type
Driverr
Datasheet

Specifications of LMH0307GRE/NOPB

Applications
Amplifiers, Video Distribution
Mounting Type
Surface Mount
Package / Case
25-Micro Array
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH0307GRETR
www.national.com
Address R/W Name
05h
06h
07h
R/W OUTPUT0CTRL
R/W OUTPUT1
R/W OUTPUT1CTRL
Bits Field
2:0
7:5
4:0
5:3
2:0
7
6
5
4
3
7
6
RSVD
FLOSOF
FLOSON
LOSEN
MUTE
SDTF0Thresh
HDTF1Thresh
AMP1
HDTF1ThreshLSB
SDTF1ThreshLSB
RSVD
SDTF1Thresh
Default Description
10000
010
100
011
010
12
0
0
0
0
0
1
1
Reserved as 0. Always write 0 to this bit.
Force LOS to always OFF in regard to its effect on the output
signal. This forces the device into either the mute or “add
offset” state. The LOS bit in register 01h still reflects the
correct state of LOS.
0: LOS operates normally, muting or adding offset as
specified by the MUTE bit.
1: Muting or adding offset is always in place as specified by
the MUTE bit.
Force LOS to always ON in regard to its effect on the output
signal. This prevents the device from muting or adding offset.
The LOS bit in register 01h still reflects the correct state of
LOS.
0: LOS operates normally, muting or adding offset as
specified in the MUTE bit.
1: Muting or adding offset never occurs.
Configures LOS to be combined with the ENABLE
functionality.
0: Only the PD bits and ENABLE pin affect the power down
state of the output drivers.
1: If the ENABLE pin is set to ground, it powers down the
output drivers regardless of the state of LOS or the PD bits.
With the ENABLE pin set to V
output drivers, and LOS=1 will leave the power down state
dependent on the PD bits.
Selects whether the device will MUTE when loss of signal is
detected or add an offset to prevent self oscillation. When an
input signal is detected (LOS=1), the device will operate
normally.
0: Loss of signal will force a small offset to prevent self
oscillation.
1: Loss of signal will force the channel to MUTE.
Sets the Termination Fault threshold for SDO0, when SD is
set to SD rates (1). Combines with SDTF0ThreshLSB in
register 03h (default for combined value is 0101).
Sets the Termination Fault threshold for SDO1, when SD is
set to HD rates (0). Combines with HDTF1ThreshLSB in
register 07h (default for combined value is 1001).
SDO1 output amplitude in roughly 5 mV steps.
Least Significant Bit for HDTF1Thresh detection threshold.
Combines with HDTF1Thresh bits in register 06h.
Least Significant Bit for SDTF1Thresh detection threshold.
Combines with SDTF1Thresh bits in register 07h.
Reserved as 011. Always write 011 to these bits.
Sets the Termination Fault threshold for SDO1, when SD is
set to SD rates (1). Combines with SDTF1ThreshLSB in bit 6
(default for combined value is 0101).
CC
, LOS=0 will power down the

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