LMH0307GRE/NOPB National Semiconductor, LMH0307GRE/NOPB Datasheet - Page 11

IC CBL DVR DUAL HD/SD 25-UARRAY

LMH0307GRE/NOPB

Manufacturer Part Number
LMH0307GRE/NOPB
Description
IC CBL DVR DUAL HD/SD 25-UARRAY
Manufacturer
National Semiconductor
Type
Driverr
Datasheet

Specifications of LMH0307GRE/NOPB

Applications
Amplifiers, Video Distribution
Mounting Type
Surface Mount
Package / Case
25-Micro Array
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH0307GRETR
Address R/W Name
03h
04h
R/W DIRECTION
R/W OUTPUT0
Bits Field
7:5
4:0
7
6
5
4
3
2
1
0
HDTF0ThreshLSB
SDTF0ThreshLSB
RSVD
DTF1N
DTF1P
DTF0N
DTF0P
DLOS
HDTF0Thresh
AMP0
Default Description
10000
100
11
1
1
0
0
0
0
0
0
Least Significant Bit for HDTF0Thresh detection threshold.
Combines with HDTF0Thresh bits in register 04h.
Least Significant Bit for SDTF0Thresh detection threshold.
Combines with SDTF0Thresh bits in register 05h.
Reserved as 0. Always write 0 to this bit.
Direction of TF1N that affects FAULT pin (when not masked).
0: TF1N=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TF1N=0 will cause FAULT to be 0 (when the condition is
not masked off).
Direction of TF1P that affects FAULT pin (when not masked).
0: TF1P=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TF1P=0 will cause FAULT to be 0 (when the condition is
not masked off).
Direction of TF0N that affects FAULT pin (when not masked).
0: TF0N=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TF0N=0 will cause FAULT to be 0 (when the condition is
not masked off).
Direction of TF0P that affects FAULT pin (when not masked).
0: TF0P=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TF0P=0 will cause FAULT to be 0 (when the condition is
not masked off).
Direction of LOS that affects FAULT pin (when not masked).
0: LOS=0 will cause FAULT to be 0 (when the condition is not
masked off).
1: LOS=1 will cause FAULT to be 0 (when the condition is not
masked off).
Sets the Termination Fault threshold for SDO0, when SD is
set to HD rates (0). Combines with HDTF0ThreshLSB in
register 03h (default for combined value is 1001).
SDO0 output amplitude in roughly 5 mV steps.
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