MAX7365 Maxim, MAX7365 Datasheet - Page 13

• Manufacturer Part Number: MAX7365
• Description: The MAX7365 is an I²C-interfaced peripheral that provides microprocessors with management of up to 56 key switches
• Manufacturer: Maxim

One data bit is transferred during each clock pulse
(Figure
SCL is high.
The acknowledge bit is a clocked 9th bit
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse; therefore, the SDA line is stable low during the
high period of the clock pulse. When the master is trans-
mitting to the device, the device generates the acknowl-
edge bit because the device is the recipient. When the
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device has a 7-bit long slave address of 0x70, 0x72,
0x74, or 0x76 as determined by the suffix of the complete
part number. The bit following a 7-bit slave address is the
Figure 3. Bit Transfer
Figure 4. Acknowledge
3). The data on SDA must remain stable while
SDA
SCL
TRANSMITTER
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RECEIVER
SDA BY
SDA BY
SCL
CONDITION
START
Key-Switch Controller with GPIO Ports
S
DATA LINE STABLE;
DATA VALID
Slave Addresses
Acknowledge
(Figure
Bit Transfer
1
4), which
CHANGE OF DATA
ALLOWED
2
1MHz I
R/W bit, which is low for a write command and high for a
read command.
The device monitors the bus continuously waiting for a
START condition, followed by its slave address. When
the device recognizes its slave address, it acknowledges
and is then ready for continued communication.
The device features a 20ms (min) bus timeout on the two-
wire serial interface, largely to prevent the device from
holding the SDA I/O low during a read transaction should
the SCL lock up for any reason before a serial transac-
tion is completed. Bus timeout operates by causing the
device to internally terminate a serial transaction (either
read or write) if the time between adjacent edges on SCL
exceeds 20ms. After a bus timeout, the device waits for
a valid START condition before responding to a consecu-
tive transmission. This feature can be enabled or dis-
abled under user control by writing to the Configuration
register. In sleep mode, the internal oscillator is disabled,
thus the bus timeout feature is not active.
2
C-Interfaced 8 x 7
CLOCK PULSE FOR
8
ACKNOWLEDGE
9
MAX7365
Bus Timeout