MAX7365 Maxim, MAX7365 Datasheet - Page 11

• Manufacturer Part Number: MAX7365
• Description: The MAX7365 is an I²C-interfaced peripheral that provides microprocessors with management of up to 56 key switches
• Manufacturer: Maxim

The GPIO Value register consists of a read and write mode
for the GPIO4–GPIO0 pins
ister reports the debounced input values for ports config-
ured as a GPI. There is one debounce period delay prior
to detecting a transition on the input port. This prevents a
false interrupt from occurring when changing a port from
an output to an input. This register reports the state of all
input ports, regardless of any interrupt mask settings.
When written, this register sets the output as logic-low
when written logic 0, or as logic-high when written logic
1 for ports configured as GPO.
The GPIs, LSB, and MSB Interrupt Mask registers
control which ports trigger an interrupt
GPIO4–GPIO0,
GPI[14:8]). Set the bit to logic 0 to enable the interrupt.
Set the bit to logic 1 to mask the interrupt.
If the port that generated the interrupt is not masked, then
the interrupt causes the INT signal to assert. A read of the
port value registers (0x33 to 0x35) is required to deassert
the INT pin. Note that transitions that occur while INT is
asserted, but before the read of the port value registers,
set the appropriate bit of the port value registers only, but
have no affect on the INT pin as it is already asserted.
However, transitions that occur when the I
cannot be latched into the port values registers until
after the read has taken place. If there are transitions
that cause the INT signal to assert during the time of an
I
read transaction has taken place. Note that the interrupt
configurations only apply when a port is configured as
an input.
The GPIs, LSB, and MSB Interrupt Trigger registers
control how an interrupt is triggered
GPIO4–GPIO0,
GPI[14:8]). Set the bit to logic 0 for rising edge-triggered
interrupts. Set the bit to logic 1 for both rising and falling
edge-trigged interrupts.
2
C read, they cause the INT signal to reassert once the
GPIs, LSB, MSB Interrupt Trigger Registers
GPIs, LSB, MSB Interrupt Mask Registers
Table 19
Table 22
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(Table
for GPI[7:0], and
for GPI[7:0], and
GPIO Value Register (0x35)
Key-Switch Controller with GPIO Ports
17). When read, this reg-
(0x39, 0x3A, 0x3B)
(0x36, 0x37, 0x38)
(Table 21
(Table 18
Table 20
Table 23
2
C is active
for
for
for
for
1MHz I
This register allows for high-side open-drain mode for
GPIO4–GPIO0 (see
low-side open-drain mode. Set the bit to logic 1 to enable
high-side open-drain mode.
This register enables the GPO 100kI pullup resistor in
low-side open-drain mode or pulldown resistor in high-
side open-drain mode for GPIO4–GPIO0
the bit to logic 0 to disable the internal pullup. Set the bit
to logic 1 to enable the internal pullup.
The GPIO Global Configuration register controls the main
settings for the GPIO ports
interrupt generation for I
bit for the GPIs. Set bit D4 to logic 1 for normal GPIO oper-
ation for GPIO_, and ROW_ and COL_ configured as GPIs.
GPIO_ configured as GPOs are automatically enabled.
The GPI Debounce Setting register sets the amount of
time an input must be held in order for the device to reg-
ister a logic transition
setting is independent of the key-switch debounce set-
ting. Bits D[4:0] set the 32 possible debounce times from
9ms up to 40ms.
The I
that indicates if an I
28). Read this register to clear an I
interrupt.
Three possible sources generate INT: key-switch FIFO
level/debounce cycle settings, I
configured as inputs (registers 0x01 or 0x40, 0x39 –
0x3A). Read the respective data/status registers for each
type of interrupt to clear INT. If multiple sources generate
the interrupt, all the related status registers must be read
to clear INT.
GPO High-Side Open-Drain Enable Register (0x3C)
2
C Timeout Flag register contains a single bit (D0)
GPO Pullup/Pulldown Resister Enable Register
I
2
C Timeout Flag Register (0x48) (Read Only)
GPIO Global Configuration Register (0x40)
2
C-Interfaced 8 x 7
GPI Debounce Setting Register (0x42)
Table
2
(Table
C timeout has occurred
2
C timeouts. Bit D4 is the enable
24). Set the bit to logic 0 for
(Table
27). The GPIO debounce
2
C timeout, and GPIOs
MAX7365
26). Bit D5 enables
2
C timeout-initiated
(Table
Interrupts
25). Set
(0x3D)
(Table