DS80C411 Maxim, DS80C411 Datasheet - Page 52

• Manufacturer Part Number: DS80C411
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

Table 11. Arithmetic Accelerator Sequencing
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40-Bit Accumulator
The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiply-
and-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is
used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly
increase speed of DSP and other high-level math operations.
The accumulator can be accessed any time the multiply/accumulate status flag (MCNT1;D2h) is cleared. The
accumulator is initialized by performing five writes to the multiplier C register (MC;D5h), LSB first. The 40-bit
accumulator can be read by performing five reads of the multiplier C register, MSB first.
Ethernet Controller
The DS80C410 incorporates a 10/100Mbps Ethernet controller, which supports the protocol requirements for
operating an Ethernet/IEEE 802.3-compliant PHY device. It provides receive, transmit, and flow control
mechanisms through a media-independent interface (MII), which includes a serial management bus for configuring
external PHY devices. The MII can be configured to operate in half-duplex or full-duplex mode at either 10Mbps or
100Mbps, or can support 10Mbps ENDEC mode operation. The system clock (external clock source after internal
multiplication or division) must be a minimum of 25MHz for use of the Ethernet 100Mbps mode.
For half-duplex mode operation, the DS80C410 shares the Ethernet physical media with other stations on the
network. The DS80C410 follows the IEEE 802.3 carrier-sense multiple-access with collision detection (CSMA/CD)
method for accessing the physical media. The MAC waits until the physical carrier is idle before attempting a
transmission. Having multiple stations on the network results in the possibility of transmissions from different
stations colliding. When a collision is detected, the MAC waits some number of time slots (according to an internal
back-off timer) before attempting retransmission. Unless instructed otherwise, the MAC automatically attempts to
retransmit collided frames up to 16 times before aborting the transmit frame. As a means of flow control when
receiving data, the MAC uses a back-pressure scheme, transmitting a jamming signal to force collisions on
Not performed for 16-bit numerator.
Load MA with dividend LSB.
Load MA with dividend LSB + 1
Load MA with dividend LSB + 2
Load MA with dividend MSB.
Load MB with divisor LSB.
Load MB with divisor MSB.
Poll the MST bit until cleared.
Read MA to retrieve the quotient MSB.
Read MA to retrieve the quotient LSB + 2
Read MA to retrieve the quotient LSB + 1
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0/MCNT1 registers as required.
Poll the MST bit until cleared (9 machine cycles).
Read MA for result MSB.
Read MA for result LSB + 2.
Read MA for result LSB + 1.
Read MA for result LSB.
(9 machine cycles for 32-bit numerator)
(6 machine cycles for 16-bit numerator)
DIVIDE (32/16 or 16/16)
SHIFT RIGHT/LEFT
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Load MB with multiplier LSB.
Load MB with multiplier MSB.
Load MA with multiplicand LSB.
Load MA with multiplicand MSB.
Poll the MST bit until cleared (6 machine cycles).
Read MA for product MSB.
Read MA for product LSB + 2.
Read MA for product LSB + 1.
Read MA for product LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0.4–0 = 00000b.
Poll the MST bit until cleared (9 machine cycles).
Read MA for mantissa MSB.
Read MA for mantissa LSB + 2.
Read MA for mantissa LSB + 1.
Read MA for mantissa LSB.
Read MCNT0.4–MCNT0.0 for exponent.
MULTIPLY (16 x 16)
NORMALIZE