DS80C411 Maxim, DS80C411 Datasheet
DS80C411
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DS80C411 Summary of contents
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... Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire® Master, and 64 I/O pins. The DS80C410 and DS80C411 also include 64kBytes internal SRAM for user application storage and network stack. To enable access to the network, a full application- accessible TCP IPv4/6 network stack and OS are provided in the ROM ...
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... Soldering Temperature………………………………………………………………See IPC/JEDEC J-STD-020 Standard Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... Note 11: Following the one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a maximum at approximately 2V. Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port 0 pin is driven by an external memory source ...
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AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Clock Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier ...
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... Note 1: Figure 21 shows a detailed description and illustration of the system clock selection. Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the minimum/maximum system clock high (t MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 3.0V to 3.6V 1.8V ±10%, T CC3 ...
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PARAMETER SYMBOL Data Float After RD (P3 RHDZ PSEN) High ALE Low to Valid Data In t LLDV Port 0 Address to Valid Data t AVDV0 In Port Address, Port 4 CE, or Port 5 ...
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MULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − ...
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MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT 6 – ...
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MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − ...
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... A16 -A21 MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 12 of 102 A16 -A21 A16 -A21 ...
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MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS A16 -A21 13 of 102 A16 -A21 ...
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ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode ...
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MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V +±10%, T CC3 CC1 PARAMETER Input Instruction Float After PSEN PSEN High to Data Address, Port 4 CE, Port 5 PCE Valid RD Pulse Width (P3.7 or ...
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Note 1: AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production tested, but are guaranteed by design. Note 2: All parameters apply to both commercial and industrial temperature operation, unless ...
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NONMULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – ...
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NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT ...
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NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – ...
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... PORT 7 NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 A16 -A21 PORT 7 DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 22 of 102 A16 -A21 A16 -A21 ...
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... Note 4: This parameter quantifies the wait time for the case when no presence pulse detected. Note 5: The maximum timing figures shown apply only when an exact 1-Wire clock frequency can be achieved from the microcontroller input clock. A16 -A21 A16 -A21 = -40°C to +85°C.) ...
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OW PIN TIMING 24 of 102 ...
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PIN TIMING CHARACTERISTICS OWSTP (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Active Time for Presence Detect Active Time for Presence Detect Recovery Active Time for Write 1 Recovery (Notes 2, 3) Active Time for ...
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ETHERNET MII INTERFACE TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER TXClk Duty Cycle TXD, TX_EN Data Setup to TXClk TXD, TX_EN Data Hold from TXClk RXClk Pulse Width RXClk to RXD, RX_DV, ...
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SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Serial Port Clock Cycle Time Output Data Setup to Clock Rising Output Data Hold from Clock Rising Input Data Hold After ...
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SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH-SPEED OPERATION, TXD CLK = SYSCLK/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 102 ...
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POWER-CYCLE TIMING CHARACTERISTICS PARAMETER Crystal Startup Time (Note 1) Power-On Reset Delay (Note 2) Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 2: Reset ...
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... BLOCK DIAGRAM 1-WIRE CONTROLLER PORT LATCH PORT 5 P5.0–P5.7 DS80C410 DS80C411 P1.0–P1.7 PORT 1 SERIAL PORT 1 PORT LATCH TIMER 102 P0.0–P0.7 PORT 0 ...
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PIN DESCRIPTION PIN NAME 70 V +1.8V Core Supply Voltage CC1 12, 36, 62, V +3.3V I/O Supply Voltage CC3 87 13, 39, 63, V Digital Circuit Ground SS 88 Address Latch Enable, Output. When the MUX pin is low, ...
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... Once the momentary strong driver turns off, the port once again becomes the output (and input) high state. 32 P5.3 Port Alternate Function P5.0 C0TX CAN0 Transmit Output – Unavailable on DS80C411 31 P5.4 P5.1 C0RX CAN0 Receive Input – Unavailable on DS80C411 P5.2 T3 Timer 3 External Input 30 P5.5 P5.3 None P5.4 PCE0 Peripheral Chip Enable 0 29 P5.6 P5 ...
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... Ethernet PHY controller as a timing referenced for transferring information on the MDIO pin. MDC is a periodic 18 MDC signal that has no maximum high or low times. The minimum high and low times are 160ns each. The minimum period for MDC is 400ns independent of the period of TXClk and RXClk. FUNCTION ...
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PIN NAME MII Management Input/Output. The MII management I/O is the data pin for serial communication with the external Ethernet PHY controller read cycle, data is driven by the PHY to the MAC synchronously with 19 MDIO respect ...
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... TERMINOLOGY The term DS80C410 is used in the remainder of the document to refer to the DS80C410 and DS80C411 unless otherwise specified. DETAILED DESCRIPTION The DS80C410 network microcontroller offers the highest integration available in an 8051 device. Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire Master, and 64 I/O pins. ...
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For example, 40MHz standard operation has a machine cycle rate of 10MHz. In PMM, at the same external clock speed, software can select a 39kHz machine cycle rate, considerably reducing power ...
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... High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement contains a full description of all SFRs. Bits that are related to the CAN module become read-only bits on the DS80C411, returning logic 1 when read. Exceptions to this are: C0_I/O (P5CNT. general-purpose read/write bit on the DS80C411, but it has no effect on processor ...
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Table 1. SFR Addresses and Bit Locations REGISTER BIT 7 BIT 6 P4 P4.7/A19 P4.6/A18 SP DPL DPH DPL1 DPH1 DPS ID1 ID0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/T TL0 TL1 TH0 TH1 CKCON WD1 WD0 P1 ...
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REGISTER BIT 7 BIT 6 C0M9C MSRDY ETI C0M10C MSRDY ETI IP — PS1 SADEN0 SADEN1 C0M11C MSRDY ETI C0M12C MSRDY ETI C0M13C MSRDY ETI C0M14C MSRDY ETI C0M15C MSRDY ETI SCON1 SM0/FE_1 SM1_1 SBUF1 PMR CD1 CD0 STATUS PIP ...
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REGISTER BIT 7 BIT 6 DPL3 DPH3 DPS1 ID3 ID2 STATUS1 — — EIP EPMIP C0IP P7 P7.7/A7 P7.6/A6 TL3 TH3 T3CM TF3 TR3 SCON2 SM0/FE_2 SM1_2 SBUF2 Note: Shaded bits are timed-access protected. BIT 5 BIT 4 BIT 3 ...
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Table 2. SFR Reset Values REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 ...
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REGISTER BIT 7 BIT 6 STATUS 0 0 MCON T2CON 0 0 T2MOD 1 1 RCAP2L 0 0 RCAP2H 0 0 TL2 0 0 TH2 0 0 COR 0 1 PSW 0 0 MCNT0 0 ...
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... SRAM configurable as extended stack memory or MOVX data memory • 256 Bytes of RAM reserved for the CAN message centers (not available on the DS80C411) • 64kB embedded ROM firmware Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address bus/8-bit data bus through eight available chip enables ...
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... Port 6 control register (P6CNT; B2h) control the number of chip enables that are used and the maximum amount of program memory that can be accessed per chip enable. Tables 3 and 4 illustrate which port pins are converted to address lines or chip enables as a result of the P4CNT and P6CNT bit settings. ...
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... Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are needed in order to address the standard 16-bit (0–FFFFh) address range. Note 2: The default P4CNT.5-3 = 111b setting (4MB accessible per CE) requires only four chip enables in order to access the maximum 24-bit (0–FFFFFFh) address range. ...
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Table 6. External Memory Addressing Pin Assignments SIGNAL ADDRESS A15–A8 A7–A0 DATA D7–D0 CHIP ENABLES PCE3 PERIPHERAL CHIP PCE2 ENABLES PCE1 PCE0 Combined Program/Data Memory Access The DS80C410 can be configured to allow data memory access (MOVX) to the program ...
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Figure 1. Example External Memory Map—Merged Program/Data PROGRAM DATA MEMORY MEMORY = CE7 = CE6 = CE5 = CE4 = CE3 = CE2 ...
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Table 8. Data Pointer SFR Locations DATA POINTER DPX+DPH+DPL COMBINATION DPTR0 DPX (93h) + DPH (83h) + DPL (82h) DPTR1 DPX1 (95h) + DPH1 (85h) + DPL1 (84h) DPTR2 DPX2 (EBh) + DPH2 (F3h) + DPL2 (F2h) DPTR3 DPX3 (EDh) ...
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... The reset default of one stretch cycle results in a three-cycle MOVX for any external access. Therefore, the default off-chip RAM access is not at full speed. This is a convenience to existing designs that use slower RAM. When maximum speed is desired, software should select a stretch value of 0. When using very slow RAM or peripherals, the application software can select a larger stretch value. ...
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Table 9. Data Memory Cycle Stretch Values STRETCH MD2 MD1 MD0 VALUE (Note (Note ...
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The additional 256 Bytes of internal SRAM are used to configure and operate the 15 CAN- controller message centers. Extended Stack Pointer The DS80C410 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves ...
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Table 11. Arithmetic Accelerator Sequencing DIVIDE (32/16 or 16/16) Load MA with dividend LSB. * Load MA with dividend LSB + Load MA with dividend LSB + 2 . Load MA with dividend MSB. Load MB with ...
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Using this back-pressure scheme gives the DS80C410 control of the network or time to free up needed receive data buffers. For full-duplex mode operation, the physical media connects the DS80C410 directly to only one ...
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Buffer Control Unit The buffer control unit (BCU) serves as the central controller of all DS80C410 Ethernet activity. The BCU regulates CPU read/write activity to the Ethernet controller blocks through a series of SFRs: BCU control (BCUC; E7h), BCU data ...
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The BCU incorporates first-in-first-out receive packet register (receive FIFO) so that the CPU can access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer memory, the BCU ...
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Each CSR register is documented as follows: CSR Register: MAC Control Register Address: 00h Bit Names BLE 23 DRO OM[1: — 7 BLOMT[1:0] Reset State ...
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IF, Inverse Filtering 0 = inverse filtering disabled (default inverse filtering by the address check block enabled PB, Pass Bad Frames 0 = packet filter bit in the receive status word is set (= 1) only when error-free ...
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CSR Register: MAC Address High Register Address: 04h Bit Names: 31 — — 23 — — Reset State PADR [47:32]m MAC Physical Address [47:32]. These two ...
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CSR Register: Multicast Address High Register Address: 0Ch Bit Names: 31 HT[63] HT[62] 23 HT[55] HT[54] 15 HT[47] HT[46] 7 HT[39] HT[38] Reset State [63:32], Hash Table ...
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CSR Register: MII Address Register Address: 14h Bit Names: 31 — — 23 — — 15 PHYA [4:0] 7 PHYR [1:0] Reset State PHYA[4:0], PHY Address [4:0]. This ...
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... Upon successful transmission of a pause-control frame, the BUSY bit returns to logic pause-control frame currently being transmitted (default initiate a pause-control frame Figure 4. Pause-Control Frame SFD PREAMBLE (7) (1) (6) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PAUSE [15:8] PAUSE [7:0] — — — — — — 0 ...
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CSR Register: VLAN1 Tag Register Address: 20h Bit Names: 31 — — 23 — — Reset State VLAN1 [15:0], VLAN1 Tag Identifier [15:0]. These 16 bits ...
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CSR Register: Wake-Up Frame Filter Register Address: 28h Bit Names Reset State WUFD [31:0], Wake-Up Frame Filter Data [31:0]. These 32 bits are used ...
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... PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper synchronization, and then drives the 16-bits of read data requested. DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN TXCLK TX_EN TXD[3:0] ...
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... VLAN tag protocol ID (= 8100h) is encountered where the Length or Type is normally expected. The frame is then considered to be VLAN tagged. The VLAN frame format is described later. Figure 7. IEEE 802.3 Ethernet Frame PREAMBLE SFD DESTINATION ADDRESS (7) (1) (6) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN ETHERNET FRAME SOURCE ADDRESS TYPE/LENGTH (6) ( 102 Figure 7. ...
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Address Check Block The address check block of the Ethernet controller monitors the destination address of all incoming packets and determines whether the address passes or fails the filter criteria configured by CPU. The outcome of this address filter test, ...
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... If a non-zero match occurs between the TPID and VLAN2 register setting, the frame is recognized as having a VLAN2 tag. For VLAN2 tagged frames, the TPID is followed by 18 Bytes containing the VLAN ID; therefore, the MAC extends the maximum legal frame length by a total of 20 Bytes (TPID = 2 Bytes, VLAN Bytes). Figure 10. VLAN Tagged Frame ...
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... Figure 11. Transmit/Receive Data Buffer Memory 8kB INTERNAL SRAM RECEIVE BUFFER (n PAGES) PAGE ( BUFFER SIZE PAGE ( SETTING (EBS.4–EBS.0) TRANSMIT BUFFER ( PAGES) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PAGE 0 PAGE PAGE PAGE 31 ...
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Transmit/Receive Status Words For each attempt made by the MAC to receive or transmit packet data, the BCU writes a 32-bit transmit or receive status word back to the first word of the starting page for the packet. This word ...
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NOCRS, No Carrier. This bit is only valid in half-duplex mode transmit frame was not aborted due to lack of carrier 1 = transmit frame aborted due to lack of carrier (CRS = 0 when transmit frame initiated) ...
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... LONG, Frame Too Long. This bit only serves as a status indicator and does not cause frame truncation receive frame did not exceed the maximum frame length check 1 = receive frame exceeded the maximum frame length (1518 Bytes, unless VLAN tagged) RUNT, Runt Frame 0 = receive frame is not a runt frame (< ...
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Ethernet Interrupts The DS80C410 Ethernet controller supports two interrupt sources: Ethernet power-mode interrupt and the Ethernet activity interrupt. Each interrupt source has its own enable, priority, and flag bits. The locations of these bits are documented in the interrupt vector ...
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... NetBoot allows an application to be downloaded from the network and executed by the microcontroller. To use the ROM firmware, the system is required to have the following hardware components: • 64kB SRAM memory, internal on the DS80C410 and DS80C411, mapped (Note 1) at address locations 000000h–00FFFFh • ...
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Figure 13. ROM Code Boot Sequence Figure 13 illustrates the ROM decisions 74 of 102 ...
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... Enables CE4–7, 1M/peripheral chip enable Merged program/data CE0–3, relocate internal XRAM Enables extended 1kB stack option Configure to maximum MOVX stretch value Configure UARTs for Mode 1 serial operation Figure 14. Memory Map Following Execution of ROM_Init on DS80C410/DS80C411 INTERNAL MEMORY program CAN/BCU XRAM ROM ...
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Serial Loader The serial loader function implemented by the firmware can be invoked by leaving the serial loader pin (P1.7) at logic 1 during the boot sequence. When this condition is found, the ROM monitors the RXD0 pin for reception ...
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NetBoot The NetBoot process affords the user flexibility to download or update code remotely over the network. This capability is quite powerful. Not only does it make firmware revisions trivial, but it also makes remote diagnostics very practical. Also, since ...
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... TFTP server the file ‘TINI400.’ Using this strategy, the TFTP server operator can distinguish between different devices and/or different releases of the Maxim Networked Microcontroller ROM firmware (DS80C400, DS80C410, and DS80C411). After successfully locating the desired file on the TFTP server, the DS80C410 must transfer and program the file into memory ...
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... Figure 17. Maxim tbin2 Record and File Format tbin2 file tbin2 record tbin2 record tbin2 record tbin2 record . . . tbin2 record Find-User Code The DS80C410 ROM firmware attempts to find valid user code by searching for specific signature bytes. First, the address C000h in the internal RAM is checked. If unsuccessful, the ROM starts a search at the beginning of each 64kB block of memory ...
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ROM function. Table 16 provided by the TCP/IP stack, socket layer, and task manager are included after the table, while the full details for these and other exported ROM functions are covered in the High-Speed Microcontroller User’s Guide: Network ...
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Table 16. ROM Export Table INDEX FUNCTION 0 Num_Fn,0,0 1 crc16 2 mem_clear 3 mem_copy 4 mem_compare 5 add_dptr0 6 add_dptr1 7 sub_dptr0 8 sub_dptr1 9 getpseudorandom 10 rom_kernelmalloc 11 rom_kernelfree 12 rom_malloc 13 rom_malloc_dirty 14 rom_free 15 rom_deref 16 ...
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INDEX FUNCTION 61 task_kill 62 task_suspend 63 task_sleep 64 task_signal 65 rom_task_switch_in 66 rom_task_switch_out 67 EnterCritSection 68 LeaveCritSection 69 rom_init 70 rom_copyivt 71 rom_redirect_init 72 mm_init 73 km_init 74 ow_init 75 network_init 76 eth_init 77 init_sockets 78 tick_init 79 WOS_Tick ...
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INDEX FUNCTION 122 Math_LongDiv1024 123 task_suspend_nc 123 task_sleep_nc 124 UDP_TestReceive 125 ETH_ReadMII 126 ETH_WriteMII 127 ETH_ReadCSR 128 ETH_WriteCSR 129 IP_CheckHeader 130 IP_PacketReceived DESCRIPTION/GROUP Task scheduler functions Socket function Ethernet MAC functions IP stack functions 83 of 102 ...
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... TCP/IP Stack and Berkeley Sockets The ROM firmware implements TCP/IP Ethernet networking over an industry-standard/Berkeley socket interface. The stack supports TCP and UDP transport protocols, allowing a maximum of 24 client/server sockets for either IPv4 or IPv6. Table 17 lists the socket functions implemented and accessible in the ROM firmware. The full details of each socket function are contained in the High-Speed Microcontroller User’ ...
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... Controller Area Network (CAN) Module The DS80C410 incorporates one CAN controller that is fully compliant with the CAN 2.0B specification. On the DS80C411, the CAN controller is not available. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware ...
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Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the description of this bit in the High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement for more information. The CAN module contains a block of ...
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CAN Interrupts The DS80C410 provides one interrupt source for the CAN controller. The CAN interrupt source can be triggered by a receive/transmit acknowledgment from one of the 15 message centers or an error condition. Each message center has individual ETI ...
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Table 19. Arbitration/Masking Feature Summary ARBITRATION TEST NAME REGISTERS Message Center Standard 11-bit Arbitration Registers 0–1 Arbitration (Located in each message (CAN 2.0A) center, MOVX memory) Message Center Extended 29-bit Arbitration Registers 0–3 Arbitration (Located in each message (CAN 2.0B) ...
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... The 1-Wire bus master supports bit banging, search ROM accelerator, and overdrive modes. Detailed operation of the 1-Wire bus is described in The Book of iButton Standards (www.maxim-ic.com/iButtonBook). Communicating with the Bus Master The microcontroller interface to the 1-Wire bus master is through two SFRs, 1-Wire master address (OWMAD; ...
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Clock Control All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency for the 1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal register implements ...
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... These commands are generated through the setting of a corresponding bit in the command register (xxxxx000h). These operational modes are defined in The Book of iButton Standards available on our website at www.maxim-ic.com/iButtonBook. 1WR (Bit 0): 1-Wire Reset. Setting this bit to logic 1 causes a reset of the 1-Wire bus, which must precede any command given on the bus ...
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EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 ...
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Table 22. 1-Wire Bus Master Interrupt Sources INTERRUPT SOURCE After a 1-Wire reset has been issued, this flag is set after the amount Presence Detect of time for a presence-detect pulse to have occurred. This bit is cleared when the ...
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Timers The microcontroller provides four general-purpose timer/counters. Timers 0, 1, and 3 have three common modes of operation. Each of the three can be used as a 13-bit timer/counter, 16-bit timer/counter, or 8-bit timer/counter with auto-reload. Timer 0 can also ...
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Table 25 demonstrates that, for a 40MHz crystal frequency, the watchdog timer is capable of producing timeout 17 periods from 3.28ms (2 x 1/40MHz) to greater than one and a half seconds (1. default setting of CD1:0 (= ...
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Table 26. Interrupt Summary NAME FUNCTION PFI Power-Fail Interrupt INT0 External Interrupt 0 TF0 Timer 0 INT1 External Interrupt 1 TF1 Timer 1 TI0 or RI0 Serial Port 0 TF2 Timer 2 TI1 or RI1 Serial Port 1 INT2 External ...
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... Regardless of the configuration of the frequency multiplier, the system clock of the microcontroller can never be operated faster than 75MHz. This means that the maximum external clock source is 18.75MHz when using the 4X setting, and 37.5MHz when using the 2X setting. ...
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Changing the System Clock/Machine Cycle Clock Frequency The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to ...
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Status The STATUS (C5h) register and STATUS1 (F7h) register provide information about interrupt and serial port activity to assist in determining possible to enter PMM. The microcontroller supports three levels of interrupt priority: power-fail, high, and low. ...
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... The ring oscillator is an internal clock that can optionally provide the clock source to the microcontroller when exiting stop mode in response to an interrupt. During stop mode the crystal oscillator is halted to maximize power savings. Typically 1ms to 7ms are required for an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by contrast free-running digital oscillator that has no startup delay ...
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... Maxim DS80C410 DS80C411 25 26 REVISION HISTORY LQFP SELECTOR GUIDE PART 76 DS80C410-FNY 75 DS80C410+FNY DS80C411-FNY DS80C411+FNY +Denotes a lead(Pb)-free/RoHS-compliant device. PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages PACKAGE TYPE 100 LQFP 51 50 101 of 102 MAX ON-CHIP ...
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... © 2009 Maxim Integrated Products DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN DESCRIPTION 102 of 102 Maxim is a registered trademark of Maxim Integrated Products, Inc ...