DS1254 Maxim, DS1254 Datasheet - Page 13

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DS1254

Manufacturer Part Number
DS1254
Description
The DS1254 is a fully nonvolatile static RAM (NV SRAM) (organized as 2M words by 8 bits) with built-in real-time clock
Manufacturer
Maxim
Datasheet

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NOTES:
1) Voltage referenced to ground.
2) These parameters are sampled with a 50pF load and are not 100% tested.
3) BW is an open-drain output and, as such, cannot source current. An external pullup resistor should be
4) The DS3800 battery cap is a one-time use part, but can be removed and replaced. By design, DS3800 removal
5) t
6) t
7) t
8) t
9) WE is high for a read cycle.
10) OE = V
11) If the CE low transition occurs simultaneously with or later than the WE low transition in a write-enable-
12) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
13) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output
14) In a power-down condition, the voltage on any pin cannot exceed the voltage on V
connected to this pin for proper operation. BW can sink 10mA.
will mechanically damage the battery cap, which eliminates the accidental use of a previously attached and
possibly low-capacity battery cap.
earlier of CE or WE going high.
controlled write cycle, the output buffers remain in a high-impedance state during this period.
in a high-impedance state during this period.
buffers remain in a high-impedance state during this period.
WP
AH1
AH2
DS
is measured from the earlier of CE or WE going high.
, t
, t
specified as the logical AND of CE and WE, t
DH1
DH2
IH
are measured from WE going high.
are measured from CE going high.
or V
IL
. If OE = V
IH
during write cycle, the output buffers remain in a high-impedance state.
13 of 17
WP
is measured from the latter of CE or WE going low to the
CC
.
DS1254

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