STM1831 STMicroelectronics, STM1831 Datasheet - Page 6

• Manufacturer Part Number: STM1831
• Description: Voltage detector with sense input and external delay capacitor
• Manufacturer: STMicroelectronics

Description
1.1
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Pin descriptions
See
Power supply (V
This pin is used to provide power to the device. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between the V
device as possible.
Sense voltage input (V
Input voltage on this pin is monitored. When it drops below the threshold (V
output (RST) is asserted. If V
from V
Reset output (RST)
Reset output is asserted when the voltage on the V
(V
The STM1831 has an open drain, active-low output which sinks current when the output is
asserted. Connect a pull-up resistor from RST to any supply voltage up to 6 V (see
Figure
register a logic high, while all of the input current and leakage paths connected to the reset
output line are being supplied. A 10 kΩ pull-up is sufficient in most applications.
The advantages of open drain output include the ability to connect more open drain outputs
in parallel (wired OR connections) as well as connecting the output to a power supply
voltage other than V
Delay capacitor (C
Capacitor C
V
Any external leakage due to poor quality timing capacitors or excessive humidity may cause
a significant leakage current which extends the t
tracks between the C
possible, properly covered with solder mask and isolated from other tracks (especially V
by as great a distance as possible. Low-leakage timing capacitors (ceramic or film capacitor)
should be used.
Leave C
SEN
DET
Figure 1
voltage exceeds the V
).
SEN
4). Select a resistor value large enough to register a logic low, and small enough to
D
pin open if unused (i.e. t
input in order to minimize I
D
and
determines the delay (t
Table 1
CC
CC
D
D
)
.
)
pin and its respective timing capacitor should be as short as
for a brief overview of the signals available on this device.
SEN
DET
CC
Doc ID 18180 Rev 1
)
is close to 0 V, internal logic disconnects the voltage divider
threshold (see
CD
CD
SEN
= 0 ms).
) between reset deassertion and the moment when
current (see
CC
Figure 5
CD
and V
SEN
timing. To minimize this effect, the PCB
Figure 3
SS
input pin drops below the threshold
with calculations for more details).
pins, as close to the STM1831
and
Figure
20).
DET
), reset
STM1831
SS
)