STM811 STMicroelectronics, STM811 Datasheet - Page 7

• Manufacturer Part Number: STM811
• Description: Active Low, Push-Pull
• Manufacturer: STMicroelectronics

Specifications of STM811

• Operating Temperature: –40 °C to 85 °C (industrial grade)

STM809/810/811/812
2
2.1
2.2
2.3
Operation
Reset output
The STM809/810/811/812 microprocessor reset circuit asserts a reset signal to the MCU
whenever V
(MR) is taken low (see
guaranteed valid down to V
During power-up, once V
the reset time-out period, t
If V
low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V
active-low reset (RST) and active-high reset (RST) both source and sink current.
Push-button reset input (STM811/812)
A logic low on MR asserts RST. RST remains asserted while MR is low, and for t
returns high. The MR input has an internal 20 kΩ pull-up resistor, allowing it to be left open if
not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector
outputs. Connect a normally open push-button switch from MR to GND to create a manual
reset function; external debounce circuitry is not required. If the device is used in a noisy
environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise
immunity.
Negative-going V
The STM809/810/811/812 are relatively immune to negative-going V
Figure 12 on page 11
(for which the STM809/810/811/812 will NOT generate a reset pulse). The graph was
generated using a negative pulse applied to V
threshold and ending below it by the magnitude indicated (comparator overdrive). The graph
indicates the maximum pulse width a negative V
reset pulse. As the magnitude of the transient increases (further below the threshold), the
maximum allowable pulse width decreases. Any combination of duration and overdrive
which lies under the curve will NOT generate a reset signal. Typically, a V
goes 100 mV below the reset threshold and lasts 20 µs or less will not cause a reset pulse.
A 0.1 µF bypass capacitor mounted as close as possible to the V
transient immunity.
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
goes below the reset threshold (V
shows typical transient duration versus reset comparator overdrive
Figure 14 on page
CC
CC
rec
CC
exceeds the reset threshold an internal timer keeps RST low for
. After this interval, RST returns high.
transients
= 1 V (0° to 70°C).
Doc ID 9873 Rev 5
13). RST (active high for STM810/812) is
CC
CC
, starting at 0.5V above the actual reset
RST
CC
transient can have without causing a
CC
), or when the push-button reset input
returns above the reset threshold. The
goes below the reset threshold, the
CC
CC
pin provides additional
transients (glitches).
CC
transient that
rec
Operation
after it
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