STM6315 STMicroelectronics, STM6315 Datasheet - Page 7

• Manufacturer Part Number: STM6315
• Description: Open Drain Microprocessor Reset
• Manufacturer: STMicroelectronics

Specifications of STM6315

• Operating Temperature: -40 to +125˚C

2
2.1
2.2
2.3
Operation
Reset output
The STM6315 Microprocessor Reset Circuit has an active-low, open drain reset output. This
output structure will sink current when RST is asserted. Connect a pull-up resistor from RST
to any supply voltage up to 6V (see
enough to register a logic low, and small enough to register a logic high while supplying all
input current and leakage paths connected to the reset output line. A 10k pull-up is sufficient
in most applications.
The STM6315 asserts a reset signal to the MCU whenever V
threshold (V
Figure 6 on page
During power-up, (once V
for the reset time-out period, t
If V
low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V
Manual reset input
A logic low on MR asserts RST. RST remains asserted while MR is low, and for t
returns high. The MR input has an internal pull-up resistor 63kΩ (typ), allowing it to be left
open if not used.
This input can be driven with TTL/CMOS-logic levels or with open drain/collector outputs.
Connect a standard open push-button switch from MR to V
function (see
used in a noisy environment, connect a 0.1µF capacitor from MR to V
additional noise immunity.
Negative-going V
The STM6315 is relatively immune to negative-going V
page 11
STM6315 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to V
by the magnitude indicated (Reset Threshold Overdrive). The graph indicates the maximum
pulse width a negative V
magnitude of the transient increases (further below the threshold), the maximum allowable
pulse width decreases. Any combination of duration and overdrive which lies under the
curve will NOT generate a reset signal (see
as close as possible to the V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
shows typical transient duration versus reset comparator overdrive (for which the
RST
Figure 4 on page
), or when the manual reset input (MR) is taken low (see
8). RST is guaranteed valid down to V
CC
, starting at 0.5V above the actual reset threshold and ending below it
CC
CC
CC
transient can have without causing a reset pulse. As the
CC
exceeds the reset threshold) an internal timer keeps RST low
rec
transients
6); external debounce circuitry is not required. If the device is
pin provides additional transient immunity.
. After this interval, RST returns high.
Figure 4 on page
Figure
CC
12). A 0.1µF bypass capacitor mounted
CC
6). Select a resistor value large
returns above the reset threshold.
CC
goes below the reset threshold, the
CC
transients (glitches).
SS
= 1.0V.
CC
to create a manual reset
goes below the reset
SS
to provide
Figure 5
Figure 12 on
rec
and
after it
7/21