STM706 STMicroelectronics, STM706 Datasheet - Page 11

• Manufacturer Part Number: STM706
• Description: 5V Supervisor
• Manufacturer: STMicroelectronics

Specifications of STM706

• Operating Temperature: –40 °C to 85 °C (industrial grade)

STM705, STM706, STM707, STM708, STM813L
3
3.1
3.2
3.3
Note:
Operation
Reset output
The STM705/706/707/708/813L supervisor asserts a reset signal to the MCU whenever
V
MR), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic
low (logic high for STM707/708/813L) for V
85 °C.
During power-up, once V
the reset time-out period, t
If V
low for at least the reset time-out period (t
the internal timer clears. The reset timer starts when V
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure
to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V
not used.
Watchdog input (STM705/706/813L)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
timer is cleared by either:
1.
2.
See
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
CC
CC
Figure 30
goes below the reset threshold (V
a reset pulse, or
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (t
connected to MR.
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
29) after it returns high. The MR input has an internal 40
for STM705/706/813L.
CC
rec
exceeds the reset threshold an internal timer keeps RST low for
. After this interval RST returns high.
Doc ID 10520 Rev 9
RST
WD
rec
), a watchdog time-out occurs (if WDO is tied to
CC
). Any time V
(1.6 s), the reset is asserted. The internal 1.6s
< V
RST
down to V
CC
CC
returns above the reset threshold.
goes below the reset threshold
CC
pull-up resistor, allowing it
=1 V for T
WD
+ t
rec
A
), if WDO is
= 0 °C to
Operation
CC
rec
when
(see
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