STM1001 STMicroelectronics, STM1001 Datasheet - Page 7

• Manufacturer Part Number: STM1001
• Description: Active Low, Open Drain
• Manufacturer: STMicroelectronics

STM1001
2
2.1
2.2
Operation
Reset output
The STM1001 microprocessor reset circuit asserts a reset signal to the MCU whenever V
goes below the reset threshold (V
70 °C).
During power-up, once V
the reset time-out period, t
If V
low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V
active-low reset (RST) is an open drain output.
Negative-going V
The STM1001 is relatively immune to negative-going V
page 10
STM1001 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to V
by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse
width a negative V
the transient increases (further below the threshold), the maximum allowable pulse width
decreases. Any combination of duration and overdrive which lies under the curve will NOT
generate a reset signal. Typically, a V
threshold and lasts 20 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor
mounted as close as possible to the V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
shows typical transient duration versus reset comparator overdrive (for which the
CC
CC
, starting at 0.5 V above the actual reset threshold and ending below it
transient can have without causing a reset pulse. As the magnitude of
CC
CC
rec
exceeds the reset threshold an internal timer keeps RST low for
. After this interval, RST returns high.
Doc ID 10373 Rev 6
transients
RST
CC
). RST is guaranteed valid down to V
CC
transient that goes 100 mV below the reset
pin provides additional transient immunity.
CC
CC
returns above the reset threshold. The
CC
goes below the reset threshold, the
transients (glitches).
CC
= 1 V (0° to
Figure 10 on
Operation
7/18
CC