LD39300XX STMicroelectronics, LD39300XX Datasheet

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LD39300XX

Manufacturer Part Number
LD39300XX
Description
Ultra low drop BICMOS voltage regulator
Manufacturer
STMicroelectronics
Datasheet

Specifications of LD39300XX

Fixed And Adj Output Voltages
1.22V, 1.8V, 2.5V, 3.3V, ADJ. (*see order code)
Temperature Range
-40 to 125°C
Feature summary
Typical application
Order codes
January 2007
3A Guaranteed output current
Ultra low dropout voltage (200mV typ. @ 3A
load, 40mV typ. @600mA load)
Very low quiescent current (1.2mA typ. @ 3A
load, 1µA max @ 25°C in off mode)
Logic-controlled electronic shutdown
Current and thermal internal limit
±
Fixed and ADJ output voltages: 1.22V, 1.8V,
2.5V, 3.3V, ADJ. (*see order code)
Temperature range: -40 to 125°C
Fast dynamic response to line and load
changes
Stable with ceramic capacitor (see paragraph
7.1, 7.2, 7.3)
Available in PPAK and DPAK
Microprocessor power supply
DSPs power supply
Post regulators for switchin suppliers
High efficiency linear regulator
1.5% Output voltage tolerance @ 25°C
LD39300DT12-R
LD39300DT18-R
LD39300DT25-R
LD39300DT33-R
DPAK
Part numbers
Ultra low drop BICMOS voltage regulator
LD39300PT18-R
LD39300PT25-R
LD39300PT33-R
LD39300PT-R
PPAK
Rev. 1
Description
The LD39300 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
PPAK
ADJ From 1.22 to 5.0V
Output voltage
1.22V
1.8V
2.5V
3.3V
LD39300
DPAK
www.st.com
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LD39300XX Summary of contents

Page 1

Feature summary ■ 3A Guaranteed output current ■ Ultra low dropout voltage (200mV typ load, 40mV typ. @600mA load) ■ Very low quiescent current (1.2mA typ load, 1µA max @ 25°C in off mode) ■ Logic-controlled ...

Page 2

Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

LD39300 1 Diagram Figure 1. Block diagram (*) Not present on ADJ Versions Diagram 3/17 ...

Page 4

Pin configuration 2 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK) PPAK Table 1. Pin description Pln N° Symbol PPAK DPAK V /N.C. For fixed versions: Not Connected on PPAK SENSE 5 ADJ ...

Page 5

LD39300 3 Typical application circuits (C and C Capacitors must be placed as close as possible to the IC pins Figure 3. LD39300 Fixed version with inhibit 1 Inhibit Pin is not internally pulled down/up then it must ...

Page 6

Typical application circuits Figure 5. LD39300 DPAK Figure 6. Timing diagram 6/17 LD39300 ...

Page 7

LD39300 4 Maximum ratings Table 2. Absolute maximum ratings Symbol V DC Input voltage I V INHIBIT Input voltage INH V DC Output voltage O V ADJ Pin voltage ADJ I Output current O P Power dissipation D T Storage ...

Page 8

Electrical characteristics 5 Electrical characteristics Table 4. Electrical characteristics (T = 25° specified) Symbol Parameter V Operating input voltage I V Output voltage tolerance O V Reference voltage REF Output voltage LINE ∆V O regulation ...

Page 9

LD39300 6 Typical performance characteristics (T = 25° specified) Figure 7. Output voltage vs temperature Figure 9. Dropout voltage vs output current Figure 11. Quiescent current vs temperature +1V 1µ 4.7µF, ...

Page 10

Typical performance characteristics Figure 13. Output voltage vs input voltage Figure 15. Stability region vs C ESR zoom area) Figure 17. Load transient (rise time 5V 3.3V 10mA to 3A ...

Page 11

LD39300 7 Application notes 7.1 External capacitors The LD39300 requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 14. Figure 15. the relative pins and ...

Page 12

Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and ...

Page 13

LD39300 DIM. MIN. A 2.2 A1 0.9 A2 0.03 B 0.4 B2 5.2 C 0. 4.9 G1 2. PPAK MECHANICAL DATA mm. ...

Page 14

Package mechanical data DIM. MIN. A 2.2 A1 0.9 A2 0.03 B 0.64 b4 5.2 C 0. 4 (L1 0.6 14/17 DPAK MECHANICAL DATA ...

Page 15

LD39300 Tape & Reel DPAK-PPAK MECHANICAL DATA DIM. MIN 12 6.80 Bo 10.40 Ko 2.55 Po 3.9 P 7.9 mm. TYP MAX. 330 13.0 13.2 0.504 0.795 2.362 22.4 6.90 7.00 0.268 ...

Page 16

Revision history 9 Revision history Table 5. Revision history Date Revision 26-Jan-2007 1 16/17 Initial release. Changes LD39300 ...

Page 17

... LD39300 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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