STCF05 STMicroelectronics, STCF05 Datasheet - Page 16

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STCF05

Manufacturer Part Number
STCF05
Description
HIGH POWER WHITE LED DRIVER WITH I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of STCF05

Flash Mode
up to 400 mA
Torch Mode
up to 120 mA
I²C bus interface
Figure 5.
8.3
Figure 6.
8.4
16/33
Timing diagram on I²C bus
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Bit transfer
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case, the master
transmitter can generate the STOP information in order to abort the transfer. The STCF05
won't generate the acknowledge if the V
Figure
Doc ID 15257 Rev 4
7). The peripheral (STCF05) that acknowledges has to
I
supply is below the undervoltage lockout threshold.
STCF05

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