ST7MC1K2 STMicroelectronics, ST7MC1K2 Datasheet - Page 205
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ST7MC1K2
Manufacturer Part Number
ST7MC1K2
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC1K2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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MOTOR CONTROLLER (Cont’d)
10.6.10.5 Repetition Down-Counter
Both in center-aligned and edge-aligned modes,
the four Compare registers (one Compare 0 and
three for the U, V and W phases) are updated
when the PWM counter underflow or overflow and
the 8-bit Repetition down-counter has reached ze-
ro.
This means that data are transferred from the
preload compare registers to the compare regis-
ters every N cycles of the PWM Counter, where N
is the value of the 8-bit Repetition register in edge
-aligned mode. When using center-aligned mode,
the repetition down-counter is decremented every
time the PWM counter overflows or underflows. Al-
though this limits the maximum number of repeti-
tion to 128 PWM cycles, this makes it possible to
update the duty cycle twice per PWM period. As a
result, the effective PWM resolution in that case is
equal to the resolution we can get using edge-
Figure 122. Update rate examples depending on mode and MREP register settings
re-synchronization
MREP = 0
MREP = 1
MREP = 2
MREP = 3
MREP = 3
12-bit PWM
and
Counter
U
U Event: Preload registers transferred to active registers and PWM interrupt generated
U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal
U
U
U
U
U
(by SW)
Center-aligned mode
to MCP0.
aligned mode, i.e. one T
ing compare registers only once per PWM period
in center-aligned mode, maximum resolution is
2xT
The repetition down counter is an auto-reload
type; the repetition rate will be maintained as de-
fined by the MREP register value (refer to
122).
10.6.10.6 PWM interrupt generation
A PWM interrupt is generated synchronously with
the “U” update event, which allows to refresh com-
pare values by software before the next update
event. As a result, the refresh rate for phases duty
cycles is directly linked to MREP register setting.
A signal reflecting the update events may be out-
put on a standard I/O port for debugging purposes.
Refer to
tails.
mtc
, due to the symmetry of the pattern.
section10.6.7.3 on page 172
(by SW)
Edge-aligned mode
ST7MC1xx/ST7MC2xx
mtc
period. When refresh-
for more de-
205/309
Figure
1
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